Abstract: A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.

Abstract: As an opening exposing a surface of an element-forming region positioned in a region lying between two gate electrodes, a first opening is formed based on a resist pattern formed such that a portion of a region where the opening is formed overlaps two-dimensionally with a portion of one gate electrode. As an opening exposing a surface of one gate electrode, a second opening is formed based on a resist pattern formed such that a region where the opening is formed overlaps two-dimensionally solely with one gate electrode. Here, the first opening is covered with a non-photosensitive, organic film and the resist pattern. Thereafter, a tungsten interconnection is formed in the first and second openings. Thus, a semiconductor device, of which production cost is reduced, and in which electrical short-circuit and falling off of an interconnection are suppressed, can be obtained.

Abstract: A method of manufacturing a semiconductor device having a capacitor is obtained that improves adhesiveness between an interlayer dielectric film and a capacitor lower electrode without providing a liner material. A bottom surface of a through hole (28) and a side surface of the lower portion thereof are defined by silicon nitride films (20) and (25). The silicon nitride film (20) is formed on a silicon oxide film (19). An upper end of a contact plug (24) protrudes from the bottom surface of the through hole (28). A tungsten film (27) is formed on a silicon oxide film (26), and a ruthenium film (30) is formed on the tungsten film (27). A portion of the silicon oxide film (26) that defines the side surface of the through hole (28) is nitrided, thereby forming a modified layer (29) in the side surface of the silicon oxide film (26). The ruthenium film (30) is directly formed on the side surface and the bottom surface of the through hole (28), so that no liner material is interposed.

Abstract: As an opening exposing a surface of an element-forming region positioned in a region lying between two gate electrodes, a first opening is formed based on a resist pattern formed such that a portion of a region where the opening is formed overlaps two-dimensionally with a portion of one gate electrode. As an opening exposing a surface of one gate electrode, a second opening is formed based on a resist pattern formed such that a region where the opening is formed overlaps two-dimensionally solely with one gate electrode. Here, the first opening is covered with a non-photosensitive, organic film and the resist pattern. Thereafter, a tungsten interconnection is formed in the first and second openings. Thus, a semiconductor device, of which production cost is reduced, and in which electrical short-circuit and falling off of an interconnection are suppressed, can be obtained.

Abstract: A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.

Abstract: An isolating insulation film and a P type active region defined by the isolating insulation film are formed on a semiconductor substrate. Then, an access transistor gate electrode, driver transistor gate electrodes, and a dummy gate electrode are formed. The dummy gate electrode is formed to cover part of the active region within a region into which an N type dopant is to be implanted to form N+ source/drain regions. As a result, N+ source/drain regions are not formed under the dummy gate electrode, and the N+ source/drain regions are reduced in width. This reduces the conductance of access transistors, that is, improves a conductance ratio between the driver and access transistors.

Abstract: An isolating insulation film (1) and a P type active region (2) defined by the isolating insulation film (1) are formed on a semiconductor substrate. Then, an access transistor gate electrode (3), driver transistor gate electrodes (4a, 4b), and a dummy gate electrode (20) are formed. The dummy gate electrode (20) is formed to cover part of the active region (2) within a region (8) into which an N type dopant is to be implanted to form N+ source/drain regions (9). As a result, the N+ source/drain regions (9) are not formed under the dummy gate electrode (20), and the N+ source/drain regions (9) are reduced in width. This reduces the conductance of access transistors, that is, improves a conductance ratio between the driver and access transistors.