Abstract: A semiconductor memory device having a test circuit includes voltage detection circuits (120, 220) for detecting a test mode when a voltage higher than a normal use voltage is applied to a terminal (101, 201). When one voltage detection circuit (120) detects a test mode, a voltage switching circuit (130) renders a MOS transistor (111) conductive, a resistance (115) connected in parallel to the MOS transistor is short-circuited and a voltage lower than (1/2.multidot.Vcc) is applied to a bit line voltage supply line (9). Alternatively, when the other voltage detection circuit (220) detects the test mode, a voltage switching circuit (230) renders a MOS transistor (211) conductive, a resistance (114) connected in parallel to the MOS transistor is short-circuited, and a voltage higher than (1/2.multidot.Vcc) is applied to the bit line voltage supply line. Thus, by applying a voltage higher or lower than that for normal use on a bit line, a memory cell having a small margin can be tested in a short period of time.

Abstract: A semiconductor integrated circuit device for setting operational functions dependent on connection of a first bonding pad (20) to a power supply includes switching transistors (Q11, Q40, Q52, Q32) for resetting an input signal line (30) connected to the first bonding pad to a predetermined potential when there is no power supply potential applied to the first bonding pad immediately after turn-on of an operation power supply, at least one inverter (Q3, Q4, Q13, Q14; Q42, Q43; Q50, Q51) responsive to the turn-on of the power supply for the device, for setting and maintaining the potential on the input signal line, and switching transistors (Q12; Q32; Q41; Q52) to be turned on in response to output of the inverter, for cutting off a current path from the power supply through the bonding pad to the input signal line.

Abstract: A MOSRAM type semiconductor memory circuit in which the storage charge per bit cell is increased without a corresponding increase in per bit chip area. A potential decision circuit is provided for each bit line in the memory for setting a potential on the corresponding bit line. A boost circuit is provided for increasing the potential on each bit line in accordance with the operation of the potential decision circuit. One boost circuit may be provided for each bit line. Alternatively, a boost circuit may be provided common to all bit lines or a plurality of bit lines in the memory circuit.

Abstract: An insulated gate field-effect transistor (MOS.multidot.FET) formed as a basic element of an integrated circuit formed together with a substrate bias circuit in a semiconductor substrate having negative potential. In the substrate bias circuit, semiconductor regions (p.sup.+ -regions) having impurity concentrations higher than that of the semiconductor substrate (p-type) are formed between the semiconductor regions (n.sup.+ -region) and the semiconductor substrate (p-type) to form n.sup.+ p.sup.+ p-diodes.