Abstract: A variable resistor circuit is arranged to adjust a resistivity value between a first terminal and a second terminal thereof according to a control signal. The variable resistor circuit includes a first resistivity adjusting circuit and a second resistivity adjusting circuit. The first resistivity adjusting circuit includes a first series resistor circuit formed of a plurality of resistor elements and a first switch portion for selectively connecting one of specific nodes of the first series resistor circuit to the first terminal according to the control signal. The second resistivity adjusting circuit includes a second series resistor circuit formed of a plurality of resistor elements connected to the second terminal and a second switch portion for selectively connecting the first series resistor circuit to one of specific nodes of the second series resistor circuit according to the control signal.

Abstract: A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay time measurement signal is output. The delay time measurement signal is turned in accordance with a transition of one of the internal test signal. The semiconductor integrated circuit further includes a current generator coupled to the delay time measurement terminal, and still further includes a plurality of delay time measurement transistors coupled to the delay time measurement terminal. The delay time measurement transistors have a plurality of control electrodes coupled to the logic circuit to receive the internal test signals. Alternatively, the semiconductor integrated circuit may include an input switching circuit coupled between the logic circuit and the CUT and a pseudo test terminal coupled to the CUT and the logic circuit.

Abstract: A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay time measurement signal is output. The delay time measurement signal is turned in accordance with a transition of one of the internal test signal. The semiconductor integrated circuit further includes a current generator coupled to the delay time measurement terminal, and still further includes a plurality of delay time measurement transistors coupled to the delay time measurement terminal. The delay time measurement transistors have a plurality of control electrodes coupled to the logic circuit to receive the internal test signals. Alternatively, the semiconductor integrated circuit may include an input switching circuit coupled between the logic circuit and the CUT and a pseudo test terminal coupled to the CUT and the logic circuit.

Abstract: A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay time measurement signal is output. The delay time measurement signal is turned in accordance with a transition of one of the internal test signal. The semiconductor integrated circuit further includes a current generator coupled to the delay time measurement terminal, and still further includes a plurality of delay time measurement transistors coupled to the delay time measurement terminal. The delay time measurement transistors have a plurality of control electrodes coupled to the logic circuit to receive the internal test signals. Alternatively, the semiconductor integrated circuit may include an input switching circuit coupled between the logic circuit and the CUT and a pseudo test terminal coupled to the CUT and the logic circuit.

Abstract: A semiconductor integrated circuit capable of accurately measuring a time lag difference in operation test wiring is disclosed. It is provided with nMOS transistors in which each control terminal is connected to a signal terminal of a memory macro. Since the nMOS transistors are turned off when the test signals TCLK, TWE, and TRE are all at a low level, the potential of a pad which is connected to a drain is pulled up by a current generator. When the signal TCLK is changed to a high level, the transistor is turned on and the potential of the pad is changed to a low level. Then, a time lag from the moment at which the signal TCLK is changed to a high level to the moment at which the pad is changed to a low level is measured.

Abstract: A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay time measurement signal is output. The delay time measurement signal is turned in accordance with a transition of one of the internal test signal. The semiconductor integrated circuit further includes a current generator coupled to the delay time measurement terminal, and still further includes a plurality of delay time measurement transistors coupled to the delay time measurement terminal. The delay time measurement transistors have a plurality of control electrodes coupled to the logic circuit to receive the internal test signals. Alternatively, the semiconductor integrated circuit may include an input switching circuit coupled between the logic circuit and the CUT and a pseudo test terminal coupled to the CUT and the logic circuit.

Abstract: In order to reduce power consumption in a dynamic random access memory (DRAM), block selection information RBDATA indicating whether or not individual blocks in a memory cell array require a refresh is stored at means for latching 20-1 and 20-2. A circuit for operation prohibition 30 compares a portion RA8 of a refresh address output by a refresh counter 6 with refresh block specification signals RB (0) and RB (1) output by the circuit for latching 20-1 and 20-2, makes a decision as to whether or not the block indicated by the refresh address needs to be refreshed and prohibits an operation of an RAS system circuit 11 if it is decided that the block does not need to be refreshed. Thus, a self refresh is not performed for a block that does not need to be refreshed to achieve a reduction in power consumption.

Abstract: Column signals CL1˜CLm generated in a Y decoder circuit 31 are selectively output to a sub-register block 10S or a resister block 10R, based on enabling signals SEN and REN. Then, write-in data is stored in the sub-register block 10S or the resister block 10R or read-out data is obtained from the sub-register block 10S or the resister block 10R. By structuring in this way, it is possible to reduce the scale of a circuit of a semiconductor device and lessen the chip size.

Abstract: In order to reduce power consumption in a dynamic random access memory (DRAM), block selection information RBDATA indicating whether or not individual blocks in a memory cell array require a refresh is stored at means for latching 20-1 and 20-2. A means for operation prohibition 30 compares a portion RA8 of a refresh address output by a refresh counter 6 with refresh block specification signals RB (0) and RB (1) output by the means for latching 20-1 and 20-2, makes a decision as to whether or not the block indicated by the refresh address needs to be refreshed and prohibits an operation of an RAS system circuit 11 if it is decided that the block does not need to be refreshed. Thus, a self refresh is not performed for a block that does not need to be refreshed to achieve a reduction in power consumption.

Abstract: A level shifter K1 receives a part of a precharge generation signal Sp, raises its level to a predetermined value, and transfers it to an NMOS transistor NT1. A capacitor Cp receives a part of the output of the level shifter K1, supplies it to a first electrode of a complementary amplifier composed of a PMOS transistor PT1 and an NMOS transistor NT2, and pumps an operation power source to a predetermined value. The operation power source of the complementary amplifier is pumped by an electric charge charged in the capacitor Cp, and the level of a precharge control signal Spc is raised.

Abstract: The present invention relates to a semiconductor memory device having a memory cell array of a split-operation mode.The semiconductor memory device comprises a semiconductor chip having first through fourth sides, a first interconnection disposed along the first side of the semiconductor chip and supplied with a source potential level or a ground potential level, a second interconnection disposed along the second side opposed to the first side and supplied with the source potential level or the ground potential level, and a plurality of sub-array regions disposed between the first interconnection and the second interconnection. A plurality of memory cells and a plurality of sense amplifiers respectively connected to the memory cells are disposed in each of the sub-array regions. The memory cells and the sense amplifiers disposed in one of the sub-array regions are activated in response to the potential level supplied to the first interconnection.

Abstract: A semiconductor memory device having two or more memory blocks is disclosed. The disclosed semiconductor memory device comprises first and second memory cores, first and second output circuits and internal output lines connected to the first and second output circuits, respectively. The first and second output circuits are respectively connected to said first and second memory cores for outputting the data in response to first and second control signals, respectively. The disclosed semiconductor memory device further comprises first and second control signal generating circuits. The first and second control signal generating circuits are connected to the first and second output circuits for generating the first and second control signals to the first and second output circuits. The first and second control signal generating circuits receive first and second read signals having the active state and the inactive state that is switched in response to a read control signal.

Abstract: A voltage-boosting circuit outputs a boosted voltage at different potentials in response to a mode signal. In a first aspect of the invention, the boosted voltage is produced by two capacitors, both of which are driven when the mode signal is in a first state, and only one of which is driven when the mode signal is in a second state. In second and third aspects of the invention, the boosted voltage is changed by switching a power-supply potential fed to a capacitor in the voltage-boosting circuit. In a fourth aspect of the invention, the boosted voltage is output through two parallel switching elements, both of which switch on when the mode signal is in the first state, and only one of which switches on when the mode signal is in the second state.