Patents by Inventor Yasuki Fukui

Yasuki Fukui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6198165
    Abstract: A semiconductor device includes a wiring substrate having wiring and a solder resist for protecting the wiring, which are provided on an insulating substrate, a semiconductor chip which is mounted via the wiring protective film on the wiring substrate on a surface on the other side of the surface on which a circuit is provided to face a side of the wiring substrate on which the wiring is formed, and a wire for electrically connecting the circuit provided on the surface of the semiconductor chip and the wiring of the wiring substrate, and the surface of the solder resist and the semiconductor chip are firmly adhered to each other. In this semiconductor device, because the solder resist and the semiconductor chip are firmly adhered to each other, there arise no bubbles due to a spacing at a portion where the solder resist and the semiconductor chip are bonded with each other.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: March 6, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuhisa Yamaji, Yoshiki Sota, Yasuki Fukui
  • Patent number: 6100594
    Abstract: A first semiconductor chip is produced by affixing a thermo-compression sheet to the back surface of a wafer having a circuit formed on its front surface. The first semiconductor chip is mounted on a circuit board including an insulating substrate and a wiring layer provided on the insulating substrate so that the back surface of the first semiconductor chip faces the circuit board. A second semiconductor chip produced in the same manner as the first semiconductor chip is mounted on the first semiconductor chip with its back surface facing the first semiconductor chip. Each of the first and second semiconductor chips is wire-bonded to the wiring layer with a wire. The first and second semiconductor chips and the wire are sealed with a sealing resin. The wiring layer is connected to external connection terminals through via holes provided in the insulating substrate.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: August 8, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuki Fukui, Yoshiki Sota, Yuji Matsune, Atsuya Narai