Abstract: By using the InGaAs layer in which the In composition is graded or varied by stages for the contact resistance reducing cap layer of the recess type compound semiconductor FET as well as using the selective etching to InAs and GaAs at the time of recess etching, the recess profile can be made curvilinear without increasing the number of processes, and occurrence of the concentration of the electric field can be thereby prevented, restriction of the high breakdown voltage value due to recess profile eliminated, and high breakdown voltage achieved.

Abstract: A collimator is provided in an evaporation chamber to prevent the stray electrons from reaching a semiconductor substrate on which a film of the source is deposited. The collimator has a wall that prevent the stray electrons from reaching the evaporation object and a window that allows the gaseous evaporation source to travel to the object. The problem caused by the stray electrons can be solved with a simple structure, realizing a better evaporation process on the substrate.

Abstract: A compound semiconductor field effect transistor has a semiconductive layer made of a compound which consists of a single III group element and a single V group element or a compound which consists of two III group elements and a single V group element in the periodic table and a passivation film for protecting the surface of the semiconductive layer. This passivation film is formed of a chalcopyrite made of a compound which consists of a single I group element, a single III group element and two VI group elements or chalcopyrite made of a compound which consists of a single II group element, a single IV group element and two V group elements in the periodic table. Those chalcopyrites have lattice constants close to or equal to a lattice constant of the semiconductive layer. Those chalcopyrites have band gaps wider than that of the semiconductive layer. The semiconductive layer may be GaAs and InP. The chalcopyrite may be (Cu.sub.0.12 Ag.sub.0.88)AlS.sub.2 and (Zn.sub.0.04 Cd.sub.0.96)SiP.sub.2.

Abstract: A field-effect transistor of a recessed structure having an etch stopper layer is disclosed. The etch stopper layer is composed of gallium phosphide or aluminium arsenide. The etch stopper layer protects an underlying semiconductor active layer of a metal-semiconductor field-effect transistor or an underlying donor layer of a two-dimensional electron gas field-effect transistor during etching the cap layer for forming a recess receiving a gate electrode. In case of etch stopper layer of aluminium arsenide, the etch stopper layer can be etched by ultrapure water.

Abstract: An EEPROM cell is implemented by a field effect transistor comprising a channel layer of an intentionally undoped gallium arsenide, a carrier supplying layer formed on the channel layer and of a heavily doped n-type aluminum gallium arsenide having deep energy level, and a gate electrode formed on the carrier supplying layer, in which the deep energy level causes a current-voltage collapse phenomenon to take place due to trapping hot electrons injected from the channel layer to the carrier supplying layer in the presence of a stress voltage of about 1.2 volts between the source and drain for minimizing channel conductivity and in which the stress voltage of about 3 volts ionizes the deep energy level so as to allow recovering from the current-voltage collapse phenomenon, thereby providing the low and high channel conductivities to two logic levels.