Patents by Inventor Yasumasa Hasegawa
Yasumasa Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960618Abstract: A computer implemented method searches data. A number of processor units generates a candidate search result using an index for a data source in response to a search query by a user, wherein the candidate search result comprises files accessible by the user based on access control information in the index. The number of processor units generates a completed search result with a set of the files from the candidate search result having a confidentiality level less than or equal to a threshold confidentiality level. The number of processor units determines whether the user has access to a file in the candidate search result in which the file has the confidentiality level greater than the threshold confidentiality level for the data source. The number of processor units adds the file to the completed search result in response to the file being accessible by the user in the data source.Type: GrantFiled: September 1, 2021Date of Patent: April 16, 2024Assignee: International Business Machines CorporationInventors: Tohru Hasegawa, Shunsuke Ishikawa, Yasumasa Kajinaga, Keisuke Nitta, Daiki Tsuzuku
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Patent number: 11889207Abstract: The computation time in a solid-state imaging element that performs a convolution operation on image data is shortened and the power consumption is reduced. A plurality of pixels are arranged in a two-dimensional lattice pattern in a pixel array unit. A coefficient holding unit holds a predetermined weighting coefficient correlated with each of a pixel of interest among the plurality of pixels and a predetermined number of adjacent pixels adjacent to the pixel of interest. A scanning circuit performs control so that the adjacent pixel generates an amount of charge corresponding to the weighting coefficient correlated with the adjacent pixel and transfers the charge to the pixel of interest and performs control so that the pixel of interest generates an amount of charge corresponding to the weighting coefficient correlated with the pixel of interest and accumulates the charge together with the transferred charge.Type: GrantFiled: February 25, 2020Date of Patent: January 30, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Yasumasa Hasegawa
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Publication number: 20220402088Abstract: Cleaning water CW is supplied to the outer surface of a draining roll 10 from a pipe 70 arranged above the draining roll 10 that is in pressure contact with a contact roll 8 via a polishing belt PB. Accordingly, the cleaning water CW adheres evenly to the outer surface of the draining roll 10 in the longitudinal direction along with the rotation of the draining roll 10. Then, the cleaning water CW sufficiently adhering to the outer peripheral surface of the draining roll 10 is carried to a contact portion 90 between the draining roll 10 and the polishing belt PB, and cleans the abrasive surface of the polishing belt PB. As a result, it is possible to well reduce the occurrence of uneven cleaning on the abrasive surface, and to further improve the polishing effects of a polishing apparatus 1.Type: ApplicationFiled: September 15, 2020Publication date: December 22, 2022Applicant: MEINAN MACHINERY WORKS, INC.Inventor: Yasumasa HASEGAWA
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Publication number: 20220224846Abstract: The computation time in a solid-state imaging element that performs a convolution operation on image data is shortened and the power consumption is reduced. A plurality of pixels are arranged in a two-dimensional lattice pattern in a pixel array unit. A coefficient holding unit holds a predetermined weighting coefficient correlated with each of a pixel of interest among the plurality of pixels and a predetermined number of adjacent pixels adjacent to the pixel of interest. A scanning circuit performs control so that the adjacent pixel generates an amount of charge corresponding to the weighting coefficient correlated with the adjacent pixel and transfers the charge to the pixel of interest and performs control so that the pixel of interest generates an amount of charge corresponding to the weighting coefficient correlated with the pixel of interest and accumulates the charge together with the transferred charge.Type: ApplicationFiled: February 25, 2020Publication date: July 14, 2022Inventor: YASUMASA HASEGAWA
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Publication number: 20220075444Abstract: Provided is a voltage control device including a first neural network, a second neural network, an inference result determination unit, and a voltage determination unit, in which the inference result determination unit has a function of comparing correct answer value data held by the inference result determination unit with inference result data of the first neural network to obtain determination result data, and the voltage determination unit has a function of outputting a voltage signal lower than a voltage supplied to the first neural network and the second neural network in a case where the correct answer value data and the inference result data match, and outputting a voltage signal higher than the voltage supplied to the first neural network and the second neural network in a case where the correct answer value data and the inference result data do not match, on the basis of the determination result data.Type: ApplicationFiled: December 17, 2019Publication date: March 10, 2022Inventors: TOMOHIRO MATSUMOTO, YASUMASA HASEGAWA
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Patent number: 7239196Abstract: An R-2R resistor circuit network 12 used in a filter circuit according to the present invention has a path through which each branch current flows to a next integrating capacitor and a path through which each branch current flows to a low impedance analog midpoint (ground potential) Vss. The path can be selected by digital control bit data Bn to B0 for each branch current. By this, a frequency characteristic of a filter using an integrator as a component may be changed with an accuracy of (½n+1)(Gm1)/Cf from (½n+1)(Gm1)/Cf to ((2n+1?½n+1)(Gm1)Cf. As a result, by setting the setting bit width to 7 (n=6), a variable range of the frequency characteristic of over one hundredfold may be easily realized.Type: GrantFiled: April 4, 2005Date of Patent: July 3, 2007Assignee: Sony CorporationInventor: Yasumasa Hasegawa
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Patent number: 7061309Abstract: A transconductance-adjusting circuit includes a first VI converting circuit for converting a first reference voltage which is input to a current; a resistor for producing a voltage from the current output from the first VI converting circuit; a second VI converting circuit for outputting a current corresponding to a potential difference between the voltage produced by the resistor and a second reference voltage; an IV converting circuit for converting the current output from the second VI converting circuit to a voltage; and a feedback unit for changing operating points of an input circuit for inputting the first reference voltage of the first VI converting circuit by the voltage output from the IV converting circuit so that the potential difference is 0. The voltage output from the IV converting circuit is provided to a bias source for an input differential pair in a primary RC filter.Type: GrantFiled: September 10, 2004Date of Patent: June 13, 2006Assignee: Sony CorporationInventors: Hidetaka Kato, Yasumasa Hasegawa, Masahiro Segami
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Publication number: 20050232101Abstract: An R-2R resistor circuit network 12 used in a filter circuit according to the present invention has a path through which each branch current flows to a next integrating capacitor and a path through which each branch current flows to a low impedance analog midpoint (ground potential) Vss. The path can be selected by digital control bit data Bn to B0 for each branch current. By this, a frequency characteristic of a filter using an integrator as a component may be changed with an accuracy of (½n+1)(Gm1)/Cf from (½n+1)(Gm1)/Cf to ((2n+1?½n+1)(Gm1)Cf. As a result, by setting the setting bit width to 7 (n=6), a variable range of the frequency characteristic of over one hundredfold may be easily realized.Type: ApplicationFiled: April 4, 2005Publication date: October 20, 2005Inventor: Yasumasa Hasegawa
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Publication number: 20050062524Abstract: A transconductance-adjusting circuit includes a first VI converting circuit for converting a first reference voltage which is input to a current; a resistor for producing a voltage from the current output from the first VI converting circuit; a second VI converting circuit for outputting a current corresponding to a potential difference between the voltage produced by the resistor and a second reference voltage; an IV converting circuit for converting the current output from the second VI converting circuit to a voltage; and a feedback unit for changing operating points of an input circuit for inputting the first reference voltage of the first VI converting circuit by the voltage output from the IV converting circuit so that the potential difference is 0. The voltage output from the IV converting circuit is provided to a bias source for an input differential pair in a primary RC filter.Type: ApplicationFiled: September 10, 2004Publication date: March 24, 2005Inventors: Hidetaka Kato, Yasumasa Hasegawa, Masahiro Segami
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Patent number: 6677822Abstract: A filter circuit is provided for suppressing an increase of circuit area, enabling easy circuit design, realizing a reduction of power consumption by a common control voltage operation, and able to stably control the cut-off frequency. The filter circuit includes a differential circuit and a control circuit. The differential circuit includes a first MOS transistor connected to a first current source and a second MOS transistor connected to a second current source. The control circuit controls the out currents of the first and second current source and provides a control signal to the first and second MOS transistors.Type: GrantFiled: March 8, 2002Date of Patent: January 13, 2004Assignee: Sony CorporationInventor: Yasumasa Hasegawa
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Publication number: 20020163384Abstract: A filter circuit capable of suppressing an increase of circuit area, enabling easy circuit design, realizing a reduction of power consumption by a common control voltage operation, and able to stably control the cut-off frequency, that is, a filter circuit including a Gm-C circuit comprising a plurality of transconductors and load capacitors driven by the transconductors, where control signals (bias voltages) to be supplied to the transconductors are controlled by bias circuits in accordance with output voltages output from the transconductors and a reference voltage input from the outside so that output common-mode potentials of the transconductors become identical, the common-mode input potentials are controlled so that gm values become desired values in the transconductors, and W/L ratios of MOS transistors of a differential pair are set to be predetermined values.Type: ApplicationFiled: March 8, 2002Publication date: November 7, 2002Inventor: Yasumasa Hasegawa
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Patent number: 6188339Abstract: A differential multiplexer has first and second differential input pairs for receiving first and second input signals, a transistor for making active the first differential input pair by using as a control signal a first clock of a pair of differential first and second clocks, another transistor for making active the second differential input pair by using as a control signal the second clock, a first output terminal for outputting the first input signal if the first clock is larger than the second clock and outputting the second input signal if the second clock is larger than the first clock, and a second output terminal for outputting a paired differential signal of the signal output from the first output terminal.Type: GrantFiled: January 13, 1999Date of Patent: February 13, 2001Assignee: Fuji Photo Film Co., Ltd.Inventor: Yasumasa Hasegawa
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Patent number: 5252868Abstract: A CCD amplifier circuit including an active load type source-grounded inverting amplifier circuit which includes a driving MOS transistor, an active load MOS transistor connected to the driving MOS transistor, and a control circuit. The control circuit controls the voltage at the gate electrode of the active load MOS transistor with a control signal of low output impedance which is substantially inversely proportional to the drain-source voltage of the active load MOS transistor and level-shifted by a predetermined voltage. Further, a CCD delay line includes a floating diffusion region of predetermined impurities formed at an end of a charge-coupled device with a gate section having a predetermined fixed gate voltage, and a switched capacitor integrator for detecting the injection charge of the floating diffusion region to detect signal charges transferred to the floating diffusion region from the charge-coupled device.Type: GrantFiled: September 20, 1991Date of Patent: October 12, 1993Assignee: Fuji Photo Film Co., Ltd.Inventors: Takashi Miida, Tatsuya Hagiwara, Yasumasa Hasegawa
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Patent number: 5166799Abstract: A charge-coupled solid-state imaging device is arranged in such a manner that the pixel signal generated at each pixel is transferred through a plurality of divided transfer elements generated at each vertical charge transfer path and that the divided transferred pixel signals are synthesized at the horizontal charge transfer path and then outputted as the original pixel signal. The charge transfer capacity is therefore increased even if the width of each vertical charge transfer path is narrowed, thereby preventing blooming and dynamic range reduction. In addition, the narrowing of the width of each vertical charge transfer path allows the aperture to be increased commensurate with the degree of narrowing to thereby improve light receiving sensitivity and result in an advantageous high-resolution imaging device.Type: GrantFiled: March 14, 1991Date of Patent: November 24, 1992Assignee: Fuji Photo Film Co., Ltd.Inventors: Yasumasa Hasegawa, Tetsuo Tome, Kazuhiro Kawashiri, Kazuya Oda, Masahiro Konishi
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Patent number: 5142136Abstract: A method and system is provided for driving a charge-coupled solid-state interline imaging device which removes smear components and dark current to prevent flicker in the imaging device. The drive method and apparatus controls the drive signals so that the transfer elements of the imaging device are uniform while an optical image is being exposed. Also, a dummy scanning transfer operation is performed to the vertical and horizontal charge transfer paths after the exposure. Furthermore, the potential levels of the vertical charge transfer paths may be set to an equal level. As a result, the smear components on the vertical charge transfer paths are uniform so that the flicker in the reproduced optical image is significantly reduced.Type: GrantFiled: February 26, 1991Date of Patent: August 25, 1992Assignee: Fuji Photo Film Co., Ltd.Inventors: Yasumasa Hasegawa, Tetsuo Tome, Kazuya Oda, Masahiro Konishi
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Patent number: 4486963Abstract: A method of drying a veneer sheet is provided. The method comprises the steps of tenderizing, compressing, and drying a veneer sheet. The compressing and drying steps are performed at the same time. The tenderizing step is preferably be performed before the above two steps but may be done thereafter or at the same time. An apparatus for performing the method is also disclosed. The apparatus comprises tenderizing means, deceleration transfer means, and heating means. The deceleration and the heating means are combined into one section. A plurality of rollers are used as deceleration transfer means.Type: GrantFiled: September 28, 1982Date of Patent: December 11, 1984Assignee: Meinan Machinery Works, Inc.Inventors: Masaru Koike, Yasumasa Hasegawa, Satoru Shimosaka, Nagara Aoyama, Toshihiko Yoshizumi
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Patent number: 4473099Abstract: A method of drying a veneer sheet is provided. The method comprises the steps of tenderizing, compressing, and drying a veneer sheet. The compressing and drying steps are performed at the same time. The tenderizing step is preferably performed before the above two steps but may be done thereafter or at the same time. An apparatus for performing the method is also disclosed. The apparatus comprises tenderizing means, deceleration transfer means, and heating means. The deceleration and the heating means are combined into one section. A plurality of rollers are used as deceleration transfer means.Type: GrantFiled: August 11, 1980Date of Patent: September 25, 1984Inventors: Masaru Koike, Yasumasa Hasegawa, Satoru Shimosaka, Nagara Aoyama, Toshihiko Yoshizumi
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Patent number: 4469154Abstract: A method of drying a veneer sheet is provided. The method comprises the steps of tenderizing, compressing, and drying a veneer sheet. The compressing and drying steps are performed at the same time. The tenderizing step is preferably be performed before the above two steps but may be done thereafter or at the same time. An apparatus for performing the method is also disclosed. The apparatus comprises tenderizing means, deceleration transfer means, and heating means. The deceleration and the heating means are combined into one section. A plurality of rollers are used as deceleration transfer means.Type: GrantFiled: September 28, 1982Date of Patent: September 4, 1984Assignee: Meinan Machinery Works, Inc.Inventors: Masaru Koike, Yasumasa Hasegawa, Satoru Shimosaka, Nagara Aoyama, Toshihiko Yoshizumi
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Patent number: 4442876Abstract: A method of drying a veneer sheet is provided. The method comprises the steps of tenderizing, compressing, and drying a veneer sheet. The compressing and drying steps are performed at the same time. The tenderizing step is preferably be performed before the above two steps but may be done thereafter or at the same time. An apparatus for performing the method is also disclosed. The apparatus comprises tenderizing means, deceleration transfer means, and heating means. The deceleration and the heating means are combined into one section. A plurality of rollers are used as deceleration transfer means.Type: GrantFiled: September 28, 1982Date of Patent: April 17, 1984Assignee: Meinan Machinery Works, Inc.Inventors: Masaru Koike, Yasumasa Hasegawa, Satoru Shimosaka, Nagara Aoyama, Toshihiko Yoshizumi