Patents by Inventor Yasumichi Suzuki
Yasumichi Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7986041Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductor layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: GrantFiled: June 15, 2010Date of Patent: July 26, 2011Assignee: Renesas Electronics CorporationInventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
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Publication number: 20100252933Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductor layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: ApplicationFiled: June 15, 2010Publication date: October 7, 2010Applicant: RENESAS TECHNOLOGY CORPORATIONInventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
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Patent number: 7772700Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: GrantFiled: August 26, 2005Date of Patent: August 10, 2010Assignee: Renesas Technology Corp.Inventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
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Patent number: 7482650Abstract: For improving the filling properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (O3-TEOS) having good coverage is disposed over a columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties, even in a narrow pitch portion, between vertical MISFETs having a high aspect ratio.Type: GrantFiled: November 7, 2007Date of Patent: January 27, 2009Assignee: Renesas Technology Corp.Inventors: Tatsunori Murata, Takahiro Nakamura, Yasumichi Suzuki
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Patent number: 7372154Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: GrantFiled: December 1, 2004Date of Patent: May 13, 2008Assignee: Renesas Technology Corp.Inventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
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Publication number: 20080073711Abstract: For improving the filling properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (O3-TEOS) having good coverage is disposed over a columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties, even in a narrow pitch portion, between vertical MISFETs having a high aspect ratio.Type: ApplicationFiled: November 7, 2007Publication date: March 27, 2008Inventors: Tatsunori Murata, Takahiro Nakamura, Yasumichi Suzuki
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Patent number: 7306984Abstract: For improving the filing properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (O3-TEOS) having good coverage is disposed over columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties, even in a narrow pitch portion, between vertical MISFETs having a high aspect ratio.Type: GrantFiled: January 9, 2007Date of Patent: December 11, 2007Assignee: Renesas Technology Corp.Inventors: Tatsunori Murata, Takahiro Nakamura, Yasumichi Suzuki
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Patent number: 7259052Abstract: For improving the filling properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (O3-TEOS) having good coverage is disposed over columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties, even in a narrow pitch portion, between vertical MISFETs having a high aspect ratio.Type: GrantFiled: January 14, 2004Date of Patent: August 21, 2007Assignee: Renesas Technology Corp.Inventors: Tatsunori Murata, Takahiro Nakamura, Yasumichi Suzuki
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Patent number: 7247525Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: GrantFiled: August 26, 2005Date of Patent: July 24, 2007Assignee: Renesas Technology Corp.Inventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
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Publication number: 20070111512Abstract: For improving the filing properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (03-TEOS) having good coverage is disposed over columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties, even in a narrow pitch portion, between vertical MISFETs having a high aspect ratio.Type: ApplicationFiled: January 9, 2007Publication date: May 17, 2007Inventors: Tatsunori Murata, Takahiro Nakamura, Yasumichi Suzuki
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Patent number: 7061652Abstract: Predetermined additional information is superposed as a dot pattern on image information read by an image scanner, and the image information superposed with the additional information is modulated. The modulated information is demodulated and recorded on a recording medium to perform a series of operations, i.e., to simultaneously satisfy both pattern addition and modulation/demodulation.Type: GrantFiled: November 27, 2001Date of Patent: June 13, 2006Assignee: Canon Kabushiki KaishaInventors: Mitsuru Kurita, Katsuyoshi Maeshima, Masahiro Funada, Yasumichi Suzuki, Yoichi Takaragi, Akiko Kanno, Koichi Ishimoto
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Patent number: 7057775Abstract: Predetermined additional information is superposed as a dot pattern on image information read by an image scanner, and the image information superposed with the additional information is modulated. The modulated information is demodulated and recorded on a recording medium to perform a series of operations, i.e., to simultaneously satisfy both pattern addition and modulation/demodulation.Type: GrantFiled: October 9, 2002Date of Patent: June 6, 2006Assignee: Canon Kabushiki KaishaInventors: Mitsuru Kurita, Katsuyoshi Maeshima, Masahiro Funada, Yasumichi Suzuki, Yoichi Takaragi, Akiko Kanno, Koichi Ishimoto
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Publication number: 20060001169Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: ApplicationFiled: August 26, 2005Publication date: January 5, 2006Inventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
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Publication number: 20060001167Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: ApplicationFiled: August 26, 2005Publication date: January 5, 2006Inventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
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Patent number: 6967407Abstract: A semiconductor device capable of high speed operation with a substantially small interlayer capacitance is produced by steps of using an insulating film comprising an organic insulating film and an insulating film composed of an organometallic polymer material as an interlayer insulating film formed by coating, patterning the insulating film in a semi-thermosetting state, etching the organic insulating film as the lower layer by means of the organometallic polymer as a mask, using a plasma gas containing oxygen as the main component, and then conducting ultimate baking treatment of these insulating films.Type: GrantFiled: June 25, 2001Date of Patent: November 22, 2005Assignee: Renesas Technology Corp.Inventors: Miharu Otani, Jun Tanaka, Katsuhiko Hotta, Yasumichi Suzuki, Takashi Inoue
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Publication number: 20050093161Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: ApplicationFiled: December 1, 2004Publication date: May 5, 2005Inventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
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Patent number: 6838771Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: GrantFiled: April 11, 2003Date of Patent: January 4, 2005Assignee: Renesas Technology Corp.Inventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta
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Publication number: 20040140502Abstract: This invention is for improving filling properties between vertical MISFETs constituting a SRAM memory cell. Upon formation of vertical MISFETs over horizontal drive MISFETs and transfer MISFETs, they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (O3-TEOS) having good coverage is disposed over a columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties even in a narrow pitch portion between the vertical MISFETs having a high aspect ratio.Type: ApplicationFiled: January 14, 2004Publication date: July 22, 2004Inventors: Tatsunori Murata, Takahiro Nakamura, Yasumichi Suzuki
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Patent number: 6731399Abstract: A color image processing system is provided which receives binary image data from an external device, which generates the binary image data, so as to form color images. This system has a first mode in which a receiving side receives the same binary image signal color plane by color plane so that a color process is performed. It also has a second mode in which a printer receives binary image data in a plane sequence, which data indicates color planes corresponding to the types of coloring materials used for a printing operation of the printer, and then, the printer performs binary printing in accordance with the binary image data. An indicating device for indicating the first or second mode selects the first or second mode with respect to the binary image data from the external unit.Type: GrantFiled: June 26, 1992Date of Patent: May 4, 2004Assignee: Canon Kabushiki KaishaInventors: Yasumichi Suzuki, Yoshinori Ikeda, Satoshi Tanio, Ritsushi Tanabe
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Publication number: 20030213980Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.Type: ApplicationFiled: April 11, 2003Publication date: November 20, 2003Inventors: Jun Tanaka, Miharu Otani, Kiyoshi Ogata, Yasumichi Suzuki, Katsuhiko Hotta