Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

Abstract: Forming a solder joint between metal layers by preparing a structure having solder material placed between two metal layers and heating the structure to grow an intermetallic compound in a space between the two metal layers. Growing the intermetallic compound includes setting a first surface, in contact with the solder material between the two metal layers, to a first temperature, thereby enabling growth of the intermetallic compound; setting a second surface, in contact with the solder material between the two metal layers, to a second temperature, wherein the second temperature is higher than the first temperature; and maintaining a temperature gradient (temperature/unit thickness) between the two metal layers at a predetermined value or higher until the intermetallic compound substantially fills the space between the two metal layers.

Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

Abstract: A method of forming a structure for an interfacial alloy layer which is able to improve the electromigration (EM) resistance of a solder joint. More specifically, in this structure, a controlled interfacial alloy layer is provided on both sides of a solder joint. In order to form this structure, aging (maintenance of high-temperature conditions) is performed until an interfacial alloy layer of Cu3Sn has a thickness of at least 1.5 ?m.

Abstract: Forming a solder joint between metal layers by preparing a structure having solder material placed between two metal layers and heating the structure to grow an intermetallic compound in a space between the two metal layers. Growing the intermetallic compound includes setting a first surface, in contact with the solder material between the two metal layers, to a first temperature, thereby enabling growth of the intermetallic compound; setting a second surface, in contact with the solder material between the two metal layers, to a second temperature, wherein the second temperature is higher than the first temperature; and maintaining a temperature gradient (temperature/unit thickness) between the two metal layers at a predetermined value or higher until the intermetallic compound substantially fills the space between the two metal layers.

Abstract: Forming a solder joint between metal layers by preparing a structure having solder material placed between two metal layers and heating the structure to grow an intermetallic compound in a space between the two metal layers. Growing the intermetallic compound includes setting a first surface, in contact with the solder material between the two metal layers, to a first temperature, thereby enabling growth of the intermetallic compound; setting a second surface, in contact with the solder material between the two metal layers, to a second temperature, wherein the second temperature is higher than the first temperature; and maintaining a temperature gradient (temperature/unit thickness) between the two metal layers at a predetermined value or higher until the intermetallic compound substantially fills the space between the two metal layers.

Abstract: A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.

Abstract: A method of forming a structure for an interfacial alloy layer which is able to improve the electromigration (EM) resistance of a solder joint. More specifically, in this structure, a controlled interfacial alloy layer is provided on both sides of a solder joint. In order to form this structure, aging (maintenance of high-temperature conditions) is performed until an interfacial alloy layer of Cu3Sn has a thickness of at least 1.5 ?m.

Abstract: Problem To improve the electromigration (EM) resistance of a solder joint. Solution The present invention provides a unique structure for an interfacial alloy layer which is able to improve the electromigration (EM) resistance of a solder joint, and a unique method of forming this structure. More specifically, in this unique structure, a controlled interfacial alloy layer is provided on both sides of a solder joint. In order to form this structure, aging (maintenance of high-temperature conditions) is performed until an interfacial alloy layer of Cu3Sn has a thickness of at least 1.5 ?m.

Abstract: A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.

Abstract: A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.

Abstract: Forming a solder joint between metal layers by preparing a structure having solder material placed between two metal layers and heating the structure to grow an intermetallic compound in a space between the two metal layers. Growing the intermetallic compound includes setting a first surface, in contact with the solder material between the two metal layers, to a first temperature, thereby enabling growth of the intermetallic compound; setting a second surface, in contact with the solder material between the two metal layers, to a second temperature, wherein the second temperature is higher than the first temperature; and maintaining a temperature gradient (temperature/unit thickness) between the two metal layers at a predetermined value or higher until the intermetallic compound substantially fills the space between the two metal layers.

Abstract: A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.

Abstract: To reduce the risk of reduction in yield due to breakage of a thin wafer or a thin chip having through silicon vias (TSVs) formed therein in a chip bonding process, and to prevent warping during handling of a chip-on-wafer (CoW). Chips are bonded to a wafer having TSVs formed therein and sealed before the wafer is thinned. Subsequently, the CoW is subjected to a process of thinning the TSV wafer, a back-surface treatment, and a process of cutting the wafer into small pieces by dicing. Although thin wafers and thin chips having TSVs formed therein are difficult to handle since the chips are bonded to the wafer before thinning and the wafer is thinned and cut into small pieces while mechanical strength thereof is increased by fixing a support to the wafer, the yield of three-dimensional stacked devices can be increased.