Patents by Inventor Yasunobu Aoki
Yasunobu Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8478929Abstract: To improve the reliability of controlling overwriting of a nonvolatile memory in a data processing semiconductor device. In a data processing semiconductor device, a control unit which controls reading, writing, or erasing of data in a rewritable nonvolatile memory area has an operation mode that, referring to the input temperature data, controls a temperature range in which writing or erasing of data is performed to be narrower than the temperature range that allows reading of data in the memory area.Type: GrantFiled: December 10, 2010Date of Patent: July 2, 2013Assignee: Renesas Electronics CorporationInventors: Yasunobu Aoki, Hideo Kasai, Masamichi Fujito, Junpei Inoue
-
Patent number: 8144518Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: GrantFiled: May 3, 2011Date of Patent: March 27, 2012Assignee: Renesas Electronics CorporationInventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
-
Patent number: 8063433Abstract: A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×1020 cm?3 or less.Type: GrantFiled: April 24, 2008Date of Patent: November 22, 2011Assignee: Renesas Electronics CorporationInventors: Tetsuya Ishimaru, Yasuhiro Shimamoto, Toshiyuki Mine, Yasunobu Aoki, Koichi Toba, Kan Yasui
-
Publication number: 20110208904Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: ApplicationFiled: May 3, 2011Publication date: August 25, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
-
Publication number: 20110145521Abstract: To improve the reliability of controlling overwriting of a nonvolatile memory in a data processing semiconductor device. In a data processing semiconductor device, a control unit which controls reading, writing, or erasing of data in a rewritable nonvolatile memory area has an operation mode that, referring to the input temperature data, controls a temperature range in which writing or erasing of data is performed to be narrower than the temperature range that allows reading of data in the memory area.Type: ApplicationFiled: December 10, 2010Publication date: June 16, 2011Inventors: Yasunobu AOKI, Hideo Kasai, Masamichi Fujito, Junpei Inoue
-
Patent number: 7957195Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: GrantFiled: December 3, 2009Date of Patent: June 7, 2011Assignee: Renesas Electronics CorporationInventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
-
Publication number: 20100080058Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: ApplicationFiled: December 3, 2009Publication date: April 1, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
-
Patent number: 7646642Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: GrantFiled: October 9, 2007Date of Patent: January 12, 2010Assignee: Renesas Technology Corp.Inventors: Masamichi Fujito, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
-
Publication number: 20080265286Abstract: A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×1020 cm?3 or less.Type: ApplicationFiled: April 24, 2008Publication date: October 30, 2008Inventors: Tetsuya ISHIMARU, Yasuhiro Shimamoto, Toshiyuki Mine, Yasunobu Aoki, Koichi Toba, Kan Yasui
-
Publication number: 20080089146Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.Type: ApplicationFiled: October 9, 2007Publication date: April 17, 2008Inventors: Masamichi FUJITO, Makoto Mizuno, Takahiro Yokoyama, Kenji Kawada, Takashi Iwase, Yasunobu Aoki, Takashi Kurafuji, Tomohiro Uchiyama, Shuichi Sato, Yuji Uji
-
Patent number: 6411543Abstract: There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g.Type: GrantFiled: January 8, 2001Date of Patent: June 25, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Seiji Narui, Osamu Nagashima, Masatoshi Hasegawa, Hiroki Fujisawa, Shinichi Miyatake, Tsuyuki Suzuki, Yasunobu Aoki, Tsutom Takahashi, Kazuhiko Kajigaya
-
Patent number: 6301184Abstract: A DRAM module is applied to the system LSI which is provided with a standby mode for suppressing the whole operation thereof and an operation standby mode which permits at least the DRAM module to operate but suppresses the operation of other circuits. The above-mentioned modes as well as a substrate bias control technology are applied to the CMOS system LSI that operates on a low voltage. The system LSI is controlled to hold or not to hold data, enabling a memory of a large capacity to be mounted and consuming a sufficiently decreased amount of electric power.Type: GrantFiled: January 11, 2000Date of Patent: October 9, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Toshio Sasaki, Yoshihiko Yasu, Kazumasa Yanagisawa, Yuji Tanaka, Toshiaki Takahira, Yasuto Igarashi, Mariko Ohtsuka, Yasunobu Aoki
-
Publication number: 20010001598Abstract: There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g.Type: ApplicationFiled: January 8, 2001Publication date: May 24, 2001Inventors: Seiji Narui, Osamu Nagashima, Masatoshi Hasegawa, Hiroki Fujisawa, Shinichi Miyatake, Tsuyuki Suzuki, Yasunobu Aoki, Tsutom Takahashi, Kazuhiko Kajigaya
-
Patent number: 6201728Abstract: There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g.Type: GrantFiled: February 8, 1999Date of Patent: March 13, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Seiji Narui, Osamu Nagashima, Masatoshi Hasegawa, Hiroki Fujisawa, Shinichi Miyatake, Tsuyuki Suzuki, Yasunobu Aoki, Tsutom Takahashi, Kazuhiko Kajigaya