Patents by Inventor Yasunobu Hayashi

Yasunobu Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11856759
    Abstract: A semiconductor device includes: a semiconductor layer having a main surface; a first conductive type well region formed on a surface portion of the main surface of the semiconductor layer; a second conductive type source region formed on a surface portion of the well region; a second conductive type drain region formed on the surface portion of the well region at an interval from the source region; a planar gate structure formed on the main surface of the semiconductor layer so as to face a first conductive type channel region disposed between the source region and the drain region; and a memory structure disposed adjacent to a lateral side of the planar gate structure, and including an insulating film formed on the channel region and a charge storage film facing the channel region with the insulating film interposed between the charge storage film and the channel region.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: December 26, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Yushi Sekiguchi, Yasunobu Hayashi, Tadayuki Yamazaki
  • Publication number: 20230223916
    Abstract: An acoustic wave device includes a support substrate, a piezoelectric layer on the support substrate, and a functional element on the piezoelectric layer. The support substrate and the piezoelectric layer each have a rectangular or substantially rectangular shape in plan view from a direction normal to the support substrate. At least one corner portion of the piezoelectric layer has a curved shape or a polygonal shape.
    Type: Application
    Filed: March 23, 2023
    Publication date: July 13, 2023
    Inventors: Yasunobu HAYASHI, Sunao YAMAZAKI
  • Publication number: 20230085550
    Abstract: A semiconductor device includes: a semiconductor layer having a main surface; a first-conduction-type well region formed on a surface portion of the main surface of the semiconductor layer; a second-conduction-type first region formed on a surface portion of the well region; a second-conduction-type second region formed on the surface portion of the well region at an interval from the first region; a first-conduction-type diffusion layer formed on the surface portion of the main surface adjacent to the first region; a planar gate structure formed on the main surface of the semiconductor layer to face a first-conduction-type channel region between the first region and the second region; and a memory structure including a charge storage film arranged adjacent to a lateral side of the planar gate structure on a side of the first region.
    Type: Application
    Filed: August 30, 2022
    Publication date: March 16, 2023
    Applicant: ROHM CO., LTD.
    Inventor: Yasunobu HAYASHI
  • Patent number: 11588462
    Abstract: An acoustic wave device includes a piezoelectric layer and an interdigital transducer disposed on the piezoelectric layer. The interdigital transducer primarily includes Al and includes an additive selected from a group consisting of Nd, Sc, and Ta, and a concentration of the additive in a region opposite to a piezoelectric-layer-side region of the interdigital transducer is higher than a concentration of the additive in the piezoelectric-layer-side region of the interdigital transducer.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 21, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yasunobu Hayashi
  • Publication number: 20220376051
    Abstract: A semiconductor device includes a semiconductor layer, a source region and a drain region that are formed in the semiconductor layer and at an interval in a first direction, a gate insulating film that is formed such as to cover a channel region between the source region and the drain region, and a gate electrode that is formed on the gate insulating film and opposes the channel region across the gate insulating film. The gate insulating film has a major portion on which the gate electrode is formed and extension portions projecting outward from each of both sides of the major portion in a second direction orthogonal to the first direction and leak current suppressing electrodes are formed on the extension portions.
    Type: Application
    Filed: November 30, 2020
    Publication date: November 24, 2022
    Applicant: ROHM CO., LTD.
    Inventor: Yasunobu HAYASHI
  • Publication number: 20220247377
    Abstract: An acoustic wave device includes a piezoelectric substrate and an electrode on the piezoelectric substrate and including first and second layers. The first layer includes Al and Cu. The second layer is on a side opposite to a piezoelectric substrate side of the first layer and includes Al. The first layer includes an Al crystal and at least a portion of CuAl2 crystal grains that are provided in a direction orthogonal or substantially orthogonal to a thickness direction of the piezoelectric substrate. In the electrode, the CuAl2 crystal grains do not extend to the main surface of the second layer on a side opposite to a first layer side.
    Type: Application
    Filed: April 20, 2022
    Publication date: August 4, 2022
    Inventor: Yasunobu HAYASHI
  • Patent number: 11368138
    Abstract: An elastic wave device includes a spacer layer on or above a support substrate and outside a piezoelectric film as seen in a plan view from a thickness direction of the support substrate. A cover layer is disposed on the spacer layer. A through electrode extends through the spacer layer and the cover layer and is electrically connected to the wiring electrode. The wiring electrode includes a first section overlapping the through electrode as seen in the plan view from the thickness direction, a second section overlapping the piezoelectric film as seen in the plan view from the thickness direction, and a step portion defining a step in the thickness direction between the first section and the second section. The spacer layer includes an end portion embedded in the cover layer.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 21, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasunobu Hayashi, Takashi Yamane
  • Publication number: 20220130844
    Abstract: A memory cell formed on the surface of a p-well of a semiconductor substrate includes a drain region and a source region that are formed with a channel region therebetween; an insulating film that is formed to cover the channel region; a gate that is formed on the insulating film; sidewall spacers that are formed to be positioned at side surfaces of the gate and directly above the channel region; a salicide block film that is formed to cover a portion of the drain region, a portion of the source regio, the gat, and the sidewall spacers; a drain salicide layer and a source salicide layer that are formed at the salicide block film and on the drain region and the source region exposed from the salicide block film; and a nitride film that is formed to cover the salicide block film, the drain salicide layer, and the source salicide layer.
    Type: Application
    Filed: January 6, 2022
    Publication date: April 28, 2022
    Applicant: ROHM CO., LTD.
    Inventors: Tadayuki YAMAZAKI, Yasunobu HAYASHI, Goro SHIMIZU
  • Publication number: 20210375889
    Abstract: A semiconductor device includes: a semiconductor layer having a main surface; a first conductive type well region formed on a surface portion of the main surface of the semiconductor layer; a second conductive type source region formed on a surface portion of the well region; a second conductive type drain region formed on the surface portion of the well region at an interval from the source region; a planar gate structure formed on the main surface of the semiconductor layer so as to face a first conductive type channel region disposed between the source region and the drain region; and a memory structure disposed adjacent to a lateral side of the planar gate structure, and including an insulating film formed on the channel region and a charge storage film facing the channel region with the insulating film interposed between the charge storage film and the channel region.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 2, 2021
    Applicant: ROHM CO., LTD.
    Inventors: Yushi SEKIGUCHI, Yasunobu HAYASHI, Tadayuki YAMAZAKI
  • Patent number: 10847317
    Abstract: An electronic component that includes a substrate having a first main surface and a second main surface, an element on the first main surface of the substrate, a first contact electrode electrically connected to the element, an insulating film defining a first opening at a position that has an overlap with the first contact electrode in the plan view of the first main surface, a protective film covering the insulating film in a region including at least a part of the periphery of the first opening, and a first external electrode electrically connected to the first contact electrode and extending over the protective film.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: November 24, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasunobu Hayashi, Nobuhiro Ishida
  • Publication number: 20200287516
    Abstract: An acoustic wave device includes a piezoelectric layer and an interdigital transducer disposed on the piezoelectric layer. The interdigital transducer primarily includes Al and includes an additive selected from a group consisting of Nd, Sc, and Ta, and a concentration of the additive in a region opposite to a piezoelectric-layer-side region of the interdigital transducer is higher than a concentration of the additive in the piezoelectric-layer-side region of the interdigital transducer.
    Type: Application
    Filed: February 26, 2020
    Publication date: September 10, 2020
    Inventor: Yasunobu HAYASHI
  • Publication number: 20190288667
    Abstract: An elastic wave device includes a spacer layer on or above a support substrate and outside a piezoelectric film as seen in a plan view from a thickness direction of the support substrate. A cover layer is disposed on the spacer layer. A through electrode extends through the spacer layer and the cover layer and is electrically connected to the wiring electrode. The wiring electrode includes a first section overlapping the through electrode as seen in the plan view from the thickness direction, a second section overlapping the piezoelectric film as seen in the plan view from the thickness direction, and a step portion defining a step in the thickness direction between the first section and the second section. The spacer layer includes an end portion embedded in the cover layer.
    Type: Application
    Filed: February 13, 2019
    Publication date: September 19, 2019
    Inventors: Yasunobu HAYASHI, Takashi YAMANE
  • Publication number: 20190206627
    Abstract: An electronic component that includes a substrate having a first main surface and a second main surface, an element on the first main surface of the substrate, a first contact electrode electrically connected to the element, an insulating film defining a first opening at a position that has an overlap with the first contact electrode in the plan view of the first main surface, a protective film covering the insulating film in a region including at least a part of the periphery of the first opening, and a first external electrode electrically connected to the first contact electrode and extending over the protective film.
    Type: Application
    Filed: March 8, 2019
    Publication date: July 4, 2019
    Inventors: Yasunobu Hayashi, Nobuhiro Ishida