Patents by Inventor Yasunobu Hosokawa

Yasunobu Hosokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230352629
    Abstract: A semiconductor light-emitting element includes a semiconductor structure including an n-side semiconductor layer including a first region, a second region located on an outer periphery of the first region, and a plurality of third regions surrounded by the first region in a plan view, a light-emitting layer disposed on the first region, and a p-side semiconductor layer disposed on the light-emitting layer; a first insulating film disposed on the semiconductor structure and defining a plurality of first openings, each located above a corresponding one of the plurality of third regions and a plurality of second openings located above the p-side semiconductor layer; an n-side electrode disposed on the first insulating film and electrically connected to the n-side semiconductor layer through the plurality of first openings; at least one n-pad electrode disposed in the second region and electrically connected to the n-side electrode; a second insulating film disposed on the first insulating film and defining a pl
    Type: Application
    Filed: April 25, 2023
    Publication date: November 2, 2023
    Applicant: NICHIA CORPORATION
    Inventors: Yasunobu HOSOKAWA, Takumi OTSUKA
  • Patent number: 11626301
    Abstract: A method for manufacturing a semiconductor element includes: providing a wafer comprising first and second regions at an upper surface of the wafer, the second region being located at a periphery of the first region and being at a lower position than the first region; and forming a semiconductor layer made of a nitride semiconductor at the upper surface of the wafer. In a top-view, the first region comprises an extension portion at an end portion of the first region in a first direction that passes through the center of the wafer parallel to an m-axis of the semiconductor layer, the extension portion extending in a direction from a center of the wafer toward an edge of the wafer or in a direction from an edge of the wafer toward a center of the wafer.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 11, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Haruhiko Nishikage, Yoshinori Miyamoto, Yasunobu Hosokawa
  • Publication number: 20220029057
    Abstract: A light emitting element includes a first conductivity type semiconductor layer that is a nitride semiconductor layer containing Al and Ga. The first conductivity type semiconductor layer includes a first layer and a second layer. An Al percentage composition of the first layer is lower than an Al percentage composition of the second layer. The first conductivity type semiconductor layer has a first region and a second region. The first region is a region where the second conductivity type semiconductor layer and the active layer are stacked. The second region is exposed from the second conductivity type semiconductor layer and the active layer, and is connected to a first conductive member. A thickness of the first layer in the first region is smaller than a thickness of the first layer in the second region, or the second layer is exposed from the first layer in the first region.
    Type: Application
    Filed: July 12, 2021
    Publication date: January 27, 2022
    Applicant: NICHIA CORPORATION
    Inventor: Yasunobu HOSOKAWA
  • Patent number: 11094536
    Abstract: A method of manufacturing semiconductor elements includes: disposing a semiconductor layer made of a nitride semiconductor on a first wafer; and bonding a second wafer to the first wafer via the semiconductor layer. The first wafer has an upper surface including a first region and a second region surrounding a periphery of the first region and located lower than the first region. In a top view of the first wafer, a first distance between an edge of the first wafer and the first region of the first wafer in each of a plurality of first directions parallel to respective m-axes of the semiconductor layer is smaller than a second distance between the edge of the first wafer and the first region of the first wafer in each of a plurality of second directions parallel to respective a-axes of the semiconductor layer.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 17, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Haruhiko Nishikage, Yoshinori Miyamoto, Yasunobu Hosokawa
  • Publication number: 20210090914
    Abstract: A method for manufacturing a semiconductor element includes: providing a wafer comprising first and second regions at an upper surface of the wafer, the second region being located at a periphery of the first region and being at a lower position than the first region; and forming a semiconductor layer made of a nitride semiconductor at the upper surface of the wafer. In a top-view, the first region comprises an extension portion at an end portion of the first region in a first direction that passes through the center of the wafer parallel to an m-axis of the semiconductor layer, the extension portion extending in a direction from a center of the wafer toward an edge of the wafer or in a direction from an edge of the wafer toward a center of the wafer.
    Type: Application
    Filed: September 1, 2020
    Publication date: March 25, 2021
    Applicant: NICHIA CORPORATION
    Inventors: Haruhiko NISHIKAGE, Yoshinori MIYAMOTO, Yasunobu HOSOKAWA
  • Publication number: 20200279730
    Abstract: A method of manufacturing semiconductor elements includes: disposing a semiconductor layer made of a nitride semiconductor on a first wafer; and bonding a second wafer to the first wafer via the semiconductor layer. The first wafer has an upper surface including a first region and a second region surrounding a periphery of the first region and located lower than the first region. In a top view of the first wafer, a first distance between an edge of the first wafer and the first region of the first wafer in each of a plurality of first directions parallel to respective m-axes of the semiconductor layer is smaller than a second distance between the edge of the first wafer and the first region of the first wafer in each of a plurality of second directions parallel to respective a-axes of the semiconductor layer.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 3, 2020
    Applicant: NICHIA CORPORATION
    Inventors: Haruhiko NISHIKAGE, Yoshinori MIYAMOTO, Yasunobu HOSOKAWA
  • Patent number: 8119534
    Abstract: A substrate has at least one recess and/or protrusion formed in and/or on a surface thereof so as to scatter or diffract light generated in an active layer. The recess and/or protrusion is formed in such a shape that can reduce crystalline defects in semiconductor layers.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: February 21, 2012
    Assignee: Nichia Corporation
    Inventors: Hisanori Tanaka, Yasunobu Hosokawa, Yuuki Shibutani
  • Publication number: 20100197055
    Abstract: A substrate has at least one recess and/or protrusion formed in and/or on a surface thereof so as to scatter or diffract light generated in an active layer. The recess and/or protrusion is formed in such a shape that can reduce crystalline defects in semiconductor layers.
    Type: Application
    Filed: March 3, 2010
    Publication date: August 5, 2010
    Inventors: Hisanori TANAKA, Yasunobu Hosokawa, Yuuki Shibutani
  • Patent number: 7683386
    Abstract: A substrate has at least one recess and/or protrusion formed in and/or on a surface thereof so as to scatter or diffract light generated in an active layer. The recess and/or protrusion is formed in such a shape that can reduce crystalline defects in semiconductor layers.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: March 23, 2010
    Assignee: Nichia Corporation
    Inventors: Hisanori Tanaka, Yasunobu Hosokawa, Yuuki Shibutani
  • Publication number: 20050179130
    Abstract: A substrate (10) has at least one recess (20) and/or protrusion (21) formed on the surface thereof so as to scatter or diffract the light generated in an active layer (12). The recess and/or protrusion is formed in such a shape that can reduce crystalline defect in semiconductor layers (11, 13).
    Type: Application
    Filed: August 18, 2004
    Publication date: August 18, 2005
    Inventors: Hisanori Tanaka, Yasunobu Hosokawa, Yuuki Shibutani
  • Publication number: 20030205711
    Abstract: An N-type nitride semiconductor laminate includes a substrate, a buffer layer made of AlaGa1-aN (0.05≦a≦0.8) which is formed on a surface of the substrate, and an n-side nitride semiconductor layer which is formed on the buffer layer.
    Type: Application
    Filed: January 2, 2003
    Publication date: November 6, 2003
    Inventors: Koji Tanizawa, Yasunobu Hosokawa