Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV −1cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.

Abstract: A dielectric film 4 made of a high dielectric material with a relative permittivity of 8 or more is laid between a field plate section 9 and a channel layer 2. Tantalum oxide (Ta2O5), for example, may be used as the high dielectric material.

Abstract: A field effect transistor includes a semiconductor substrate with a channel layer being formed on its surface, a source electrode and a drain electrode formed at a distance on said semiconductor substrate, and a gate electrode placed between the source electrode and the drain electrode and making a Schottky junction with the channel layer. The gate electrode is provided with an overhanging field plate section and between the field plate section and the channel layer, there is laid a dielectric film. When the relative permittivity and the film thickness of the dielectric film are denoted by ∈ and t (nm), respectively, the following condition is satisfied 5≦∈<8, and 100<t<350.

Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV −1cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.

Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV−1 cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.

Abstract: A hetero-junctioned FET having as its conductive channel a highly mobile electron accumulated layer where electrons are one-dimensionally distributed. This FET is provided with first and second semiconductor layers which, formed on a semiconductor substrate, are different from each other in electron affinity and produce a semiconductor hetero junction, a source electrode and a drain electrode formed on either the first or second semiconductor layer, multiple fine damaged-area stripes formed near the interface of the hetero junction within the first semiconductor layer in the channel area between the source and drain electrodes, and a conductive channel of multiple fine electron accumulated-layer stripes generatred at the locations other than those facing the damaged areas near the interface of the hetero junction within the second semiconductor layer.

Abstract: A field control electrode 9 is formed over an insulating film 6 on a channel layer 2, between a gate electrode 5 and a drain electrode 8. Tantalum oxide (Ta.sub.2 O.sub.5), for example, may be used as the material for the insulating film 6.

Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 10.sup.12 eV .sup.-1 cm.sup.-2 or less, which is brought by the above pre-treatment in the insulator film deposition process.

Abstract: A semiconductor device having a plated heat sink structure is provided, in which an Au layer (5) high in thermal expansion coefficient is formed on the lower surface of a GaAs substrate (1) having a source electrode (2), a gate electrode (3) and a drain electrode (4) of a field effect transistor on the upper surface, and, a W layer (6) low in thermal expansion coefficient is formed on the lower surface of the Au layer (5). Warping of the device after mounted on a package is reduced on the ground of such a plated heat sink structure.

Abstract: A semiconductor device having a plated heat sink structure is provided, in which an Au layer (5) high in thermal expansion coefficient is formed on the lower surface of a GaAs substrate (1) having a source electrode (2), a gate electrode (3) and a drain electrode (4) of a field effect transistor on the upper surface, and, a W layer (6) low in thermal expansion coefficient is formed on the lower surface of the Au layer (5). Warping of the device after mounted on a package is reduced on the ground of such a plated heat sink structure.

Abstract: A semiconductor device having a plated heat sink structure is provided, in which an Au layer (5) high in thermal expansion coefficient is formed on the lower surface of a GaAs substrate (1) having a source electrode (2), a gate electrode (3) and a drain electrode (4) of a field effect transistor on the upper surface, and, a W layer (6) low in thermal expansion coefficient is formed on the lower surface of the Au layer (5). Warping of the device after mounted on a package is reduced on the ground of such a plated heat sink structure.

Abstract: A junction type field-effect transistor in accordance with the invention includes a multi-layer structure which includes a first undoped semiconductor layer, a first first-conductive type semiconductor layer and a second undoped semiconductor layer. These layers are deposited and epitaxially grown in this order on a surface of a semiconductor substrate. A part of the first first-conductive type semiconductor layer is exposed outside in a surface of the multi-layer structure. A second-conductive semiconductor layer is joined to the multi-layer structure through the surface of said multi-layer structure. A drain electrode line and a source electrode line are kept in ohmic contact with the second-conductive type semiconductor layer, and are disposed at opposite sides of a location at which the first first-conductive type semiconductor layer is joined to the second-conductive type semiconductor layer.

Abstract: A fabrication method of a FET that enables to realize a shorter length between a source-side edge of a recess and an opposing edge of a gate electrode at a higher accuracy than the accuracy limit of the present lithography technique, i.e., about .+-.0.1 .mu.m. After channel, carrier-supply, and contact layers are epitaxially grown on a semiconductor substrate in this order, a patterned insulator layer is formed on the contact layer. Using the insulator layer as a mask, the contact layer is isotropically etched to form a symmetrical recess on the underlying carrier-supply layer. One of the ends of the contact layer facing the symmetrical recess is etched again to make it asymmetric. During the etching processes, the underlying carrier-supply layer is almost never etched due to large etch rate differences for the contact layer and the carrier-supply layer. A patterned conductor layer is formed on the patterned insulator layer to form the gate electrode in Schottky contact with the carrier-supply layer.

Abstract: A field effect transistor comprises a current channel layer formed on an InP substrate through a buffer layer and formed of InGaAs having a lattice constant in match with that of InP, and a source electrode and a drain electrode formed on the current channel layer separately from each other and in ohmic contact with the current channel layer. An insulator layer is formed on the current channel layer between the source electrode and the drain electrode, and a gate electrode is formed on the insulator layer. The insulator layer being composed of a superlattice layer formed of alternately stacked undoped InAs thin films and undoped AlAs thin films. A ratio t.sub.1 /t.sub.2 of the thickness t.sub.1 of each one InAs thin film and the thickness t.sub.2 of one AlAs thin film adjacent to the each one InAs thin film is gradually reduced toward to an upper surface of the superlattice layer.