Patents by Inventor Yasunobu Sumida

Yasunobu Sumida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210180211
    Abstract: Provided is a method for manufacturing a group III nitride semiconductor substrate includes a substrate preparation step S10 of preparing a sapphire substrate, a heat treatment step S20 of performing a heat treatment on the sapphire substrate, a pre-flow step S30 of supplying a metal-containing gas over the sapphire substrate, a buffer layer forming step S40 of forming a buffer layer over the sapphire substrate under growth conditions of a growth temperature of 800° C. or higher and 950° C. or lower and a pressure of 30 torr or more and 200 torr or less, and a growth step S50 of forming a group III nitride semiconductor layer over the buffer layer under growth conditions of a growth temperature of 800° C. or higher and 1025° C. or lower, a pressure of 30 torr or more and 200 torr or less, and a growth speed of 10 ?m/h or more.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 17, 2021
    Inventors: Yasunobu SUMIDA, Yasuharu FUJIYAMA, Hiroki GOTO, Takuya NAKAGAWA, Yujiro ISHIHARA
  • Patent number: 11011374
    Abstract: A method for manufacturing a group III nitride semiconductor substrate includes a sapphire substrate preparation step S10 for preparing a sapphire substrate having, as a main surface, a {10-10} plane or a plane obtained by inclining the {10-10} plane at a predetermined angle in a predetermined direction; a heat treatment step S20 for performing a heat treatment over the sapphire substrate while performing a nitriding treatment or without performing the nitriding treatment; a buffer layer forming step S30 for forming a buffer layer over the main surface of the sapphire substrate after the heat treatment; and a growth step S40 for forming a group III nitride semiconductor layer, in which a growth surface has a predetermined plane orientation, over the buffer layer, in which at least one of a plane orientation of the main surface of the sapphire substrate, presence or absence of the nitriding treatment during the heat treatment, and a growth temperature in the buffer layer forming step is adjusted such that the
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: May 18, 2021
    Assignee: FURUKAWA CO., LTD.
    Inventors: Yasunobu Sumida, Yasuharu Fujiyama
  • Patent number: 10910474
    Abstract: A method for manufacturing a group III nitride semiconductor substrate includes a preparation step S10 for preparing a group III nitride semiconductor substrate having a sapphire substrate having a semipolar plane as a main surface, and a group III nitride semiconductor layer positioned over the main surface, in which a <0002> direction of the sapphire substrate and a <10-10> direction of the group III nitride semiconductor layer do not intersect at right angles in a plan view in a direction perpendicular to the main surface, and a growth step S20 for epitaxially growing a group III nitride semiconductor over the group III nitride semiconductor layer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: February 2, 2021
    Assignee: FURUKAWA CO., LTD.
    Inventors: Yasunobu Sumida, Yasuharu Fujiyama, Hiroki Goto, Takuya Nakagawa, Yujiro Ishihara
  • Publication number: 20200058490
    Abstract: A method for manufacturing a group III nitride semiconductor substrate includes a sapphire substrate preparation step S10 for preparing a sapphire substrate having, as a main surface, a {10-10} plane or a plane obtained by inclining the {10-10} plane at a predetermined angle in a predetermined direction; a heat treatment step S20 for performing a heat treatment over the sapphire substrate while performing a nitriding treatment or without performing the nitriding treatment; a buffer layer forming step S30 for forming a buffer layer over the main surface of the sapphire substrate after the heat treatment; and a growth step S40 for forming a group III nitride semiconductor layer, in which a growth surface has a predetermined plane orientation, over the buffer layer, in which at least one of a plane orientation of the main surface of the sapphire substrate, presence or absence of the nitriding treatment during the heat treatment, and a growth temperature in the buffer layer forming step is adjusted such that the
    Type: Application
    Filed: December 25, 2017
    Publication date: February 20, 2020
    Inventors: Yasunobu SUMIDA, Yasuharu FUJIYAMA
  • Publication number: 20190348504
    Abstract: A method for manufacturing a group III nitride semiconductor substrate includes a preparation step S10 for preparing a group III nitride semiconductor substrate having a sapphire substrate having a semipolar plane as a main surface, and a group III nitride semiconductor layer positioned over the main surface, in which a <0002> direction of the sapphire substrate and a <10-10> direction of the group III nitride semiconductor layer do not intersect at right angles in a plan view in a direction perpendicular to the main surface, and a growth step S20 for epitaxially growing a group III nitride semiconductor over the group III nitride semiconductor layer.
    Type: Application
    Filed: December 18, 2017
    Publication date: November 14, 2019
    Inventors: Yasunobu SUMIDA, Yasuharu FUJIYAMA, Hiroki GOTO, Takuya NAKAGAWA, Yujira ISHIHARA
  • Patent number: 8785976
    Abstract: A low-loss GaN-based semiconductor device is provided. The semiconductor device has the InzGa1-zN layer (where 0?z<1), the AlxGa1-xN layer (where 0<x<1), the InyGa1-yN layer (where 0?y<1) and the p-type InwGa1-wN layer (where 0?w<1) which are sequentially stacked on a base substrate of a C-plane sapphire substrate, etc. At a non-operating time, the two-dimensional hole gas is formed in the InyGa1-yN layer in the vicinity part of a hetero-interface between the AlxGa1-xN layer and the InyGa1-yN layer, and the two-dimensional electron gas is formed in the InzGa1-zN layer in the vicinity part of a hetero-interface between the InzGa1-zN layer and the AlxGa1-xN layer.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: July 22, 2014
    Assignees: The University of Sheffield, Powdec K.K.
    Inventors: Akira Nakajima, Sankara Narayanan Ekkanath Madathil, Yasunobu Sumida, Hiroji Kawai
  • Publication number: 20130126942
    Abstract: A low-loss GaN-based semiconductor device is provided. The semiconductor device has the InzGa1-zN layer (where 0?z<1), the AlxGa1-xN layer (where 0<x<1), the InyGa1-yN layer (where 0?y<1) and the p-type InwGa1-wN layer (where 0?w<1) which are sequentially stacked on a base substrate of a C-plane sapphire substrate, etc. At a non-operating time, the two-dimensional hole gas 15 is formed in the InyGa1-yN layer in the vicinity part of a hetero-interface between the AlxGa1-xN layer and the InyGa1-yN layer, and the two-dimensional electron gases is formed in the InzGa1-zN layer in the vicinity part of a hetero-interface between the InzGa1-zN layer and the AlxGa1-xN layer.
    Type: Application
    Filed: June 21, 2011
    Publication date: May 23, 2013
    Applicants: POWDEC K.K., THE UNIVERSITY OF SHEFFIELD
    Inventors: Akira Nakajima, Sankara Narayanan Ekkanath Madathil, Yasunobu Sumida, Hiroji Kawai
  • Publication number: 20120280363
    Abstract: The method for manufacturing a semiconductor device comprises steps of: forming a growth mask with a plurality of openings directly or indirectly upon a substrate that comprises a material differing from GaN-based semiconductor; and growing a plurality of island-like GaN-based semiconductor layers upon the substrate using the growth mask in the (0001) plane orientation in a manner such that the 1-100 direction extends in a direction parallel to the striped openings of the growth mask.
    Type: Application
    Filed: August 17, 2010
    Publication date: November 8, 2012
    Applicant: POWDEC K. K.
    Inventors: Yasunobu Sumida, Shoko Hirata, Takayuki Inada, Shuichi Yagi, Hiroji Kawai