Abstract: According to one embodiment, a memory device includes a substrate; a structure including a plurality of conductive layers stacked on the substrate; and a pillar arranged inside the structure and including a semiconductor layer that extends in a direction perpendicular to a surface of the substrate. The semiconductor layer includes a first portion on a side of an upper portion of the structure, and a second portion between the first portion and the substrate. The first portion has a thickness larger than a thickness of the second portion.

Abstract: In one embodiment, a semiconductor storage device includes a substrate, a stacked film including a plurality of first insulating layers and a plurality of electrode layers that are alternately provided on the substrate, and a second insulating layer provided on the stacked film. The device further includes a plurality of pillar portions, each of which including a first insulator, a charge storage layer, a second insulator, a first semiconductor layer and a third insulator that are sequentially provided in the stacked film and the second insulating layer. Furthermore, a width of the second insulating layer sandwiched between the pillar portions is narrower than a width of the stacked film sandwiched between the pillar portions, in at least a portion of the second insulating layer.

Abstract: A semiconductor device in an embodiment includes a substrate and a transistor. The transistor includes a source layer, a drain layer, a gate insulation film, a gate electrode, a contact plug and a first epitaxial layer. The source layer and the drain layer are provided in surface regions of the substrate, and contain an impurity. The gate insulation film is provided on the substrate between the source layer and the drain layer. The gate electrode is provided on the gate insulation film. The contact plug is provided so as to protrude to the source layer or the drain layer downward of a surface of the substrate. The first epitaxial layer is provided between the contact plug and the source layer or drain layer, and contains both the impurity and carbon.

Abstract: According to one embodiment, a memory device includes a substrate; a structure including a plurality of conductive layers stacked on the substrate; and a pillar arranged inside the structure and including a semiconductor layer that extends in a direction perpendicular to a surface of the substrate. The semiconductor layer includes a first portion on a side of an upper portion of the structure, and a second portion between the first portion and the substrate. The first portion has a thickness larger than a thickness of the second portion.

Abstract: In one embodiment, a semiconductor storage device includes a substrate, a stacked film including a plurality of first insulating layers and a plurality of electrode layers that are alternately provided on the substrate, and a second insulating layer provided on the stacked film. The device further includes a plurality of pillar portions, each of which including a first insulator, a charge storage layer, a second insulator, a first semiconductor layer and a third insulator that are sequentially provided in the stacked film and the second insulating layer. Furthermore, a width of the second insulating layer sandwiched between the pillar portions is narrower than a width of the stacked film sandwiched between the pillar portions, in at least a portion of the second insulating layer.

Abstract: In a semiconductor device, a source and a drain layers are located in a surface region of a substrate. A source crystal layer is located in a contact region of the source layer to extend to a position higher than the substrate. A drain crystal layer is located in a contact region of the drain layer to extend to a position higher than the substrate. A source contact is located on the source crystal layer. A drain contact is located on the drain crystal layer. A gate width or a gate length extends to a crystal orientation <110> of the substrate. A long side or a major axis of the source crystal layer or a long side or a major axis of the drain crystal layer extends in a direction inclined with respect to the crystal orientation <110> in a planar layout parallel to the surface of the substrate.

Abstract: In a semiconductor device, a source and a drain layers are located in a surface region of a substrate. A source crystal layer is located in a contact region of the source layer to extend to a position higher than the substrate. A drain crystal layer is located in a contact region of the drain layer to extend to a position higher than the substrate. A source contact is located on the source crystal layer. A drain contact is located on the drain crystal layer. A gate width or a gate length extends to a crystal orientation <110> of the substrate. A long side or a major axis of the source crystal layer or a long side or a major axis of the drain crystal layer extends in a direction inclined with respect to the crystal orientation <110> in a planar layout parallel to the surface of the substrate.

Abstract: In one embodiment, an ion implantation apparatus includes an ion source configured to generate an ion beam. The apparatus further includes a scanner configured to change an irradiation position with the ion beam on an irradiation target. The apparatus further includes a first electrode configured to accelerate an ion in the ion beam. The apparatus further includes a controller configured to change at least any of energy and an irradiation angle of the ion beam according to the irradiation position by controlling the ion beam having been generated from the ion source.

Abstract: In one embodiment, an ion implantation apparatus includes an ion source configured to generate an ion beam. The apparatus further includes a scanner configured to change an irradiation position with the ion beam on an irradiation target. The apparatus further includes a first electrode configured to accelerate an ion in the ion beam. The apparatus further includes a controller configured to change at least any of energy and an irradiation angle of the ion beam according to the irradiation position by controlling the ion beam having been generated from the ion source.

Abstract: According to one embodiment, the recess has a side surface and a bottom surface. The side surface is continuous with the major surface. The bottom surface is positioned lower than the major surface. The stacked body is provided above the major surface of the substrate. The stacked body includes a plurality of electrode layers stacked with an insulating body interposed. The columnar portion includes a semiconductor body and a stacked film. The semiconductor body extends in a stacking direction of the stacked body through the stacked body. The semiconductor body contacts the side surface and the bottom surface of the recess of the substrate. The stacked film includes a charge storage portion and is provided between the semiconductor body and the stacked body higher than the major surface of the substrate. The stacked film is not provided in the recess of the substrate.

Abstract: According to one embodiment, the recess has a side surface and a bottom surface. The side surface is continuous with the major surface. The bottom surface is positioned lower than the major surface. The stacked body is provided above the major surface of the substrate. The stacked body includes a plurality of electrode layers stacked with an insulating body interposed. The columnar portion includes a semiconductor body and a stacked film. The semiconductor body extends in a stacking direction of the stacked body through the stacked body. The semiconductor body contacts the side surface and the bottom surface of the recess of the substrate. The stacked film includes a charge storage portion and is provided between the semiconductor body and the stacked body higher than the major surface of the substrate. The stacked film is not provided in the recess of the substrate.

Abstract: An ion implantation apparatus includes an implantation part, a measuring part, and a controller. The ion implantation part implants ions into an implantation region located at a bottom of a concave portion provided on a semiconductor substrate. The measuring part measures an implantation amount of ions corresponding to an aspect ratio of the concave portion based on ions implanted from the implantation part thereinto, at a first position at which the semiconductor substrate is arranged when the ions are implanted into the implantation region or a second position close to the first position. The controller controls the implantation part to stop implantation of the ions into the measuring part when an accumulated amount of the implantation amount has reached a predetermined amount according to a target accumulation amount of the implantation region.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a plurality of conductive members containing a metal and provided on the substrate, a stacked body provided in each region between the conductive members, a semiconductor pillar piercing the stacked body, a memory film and internal stress films. The plurality of conductive members extend in a first direction and are separated from each other in a second direction. The internal stress films also extend in the first direction and are separated from each other in the second direction. The first direction and the second direction are parallel to an upper surface of the substrate and intersect each other. The internal stress films contain material having internal stress having the reverse polarity of internal stress of the metal.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a plurality of conductive members containing a metal and provided on the substrate, a stacked body provided in each region between the conductive members, a semiconductor pillar piercing the stacked body, a memory film and internal stress films. The plurality of conductive members extend in a first direction and are separated from each other in a second direction. The internal stress films also extend in the first direction and are separated from each other in the second direction. The first direction and the second direction are parallel to an upper surface of the substrate and intersect each other. The internal stress films contain material having internal stress having the reverse polarity of internal stress of the metal.

Abstract: An ion implantation apparatus includes an implantation part, a measuring part, and a controller. The ion implantation part implants ions into an implantation region located at a bottom of a concave portion provided on a semiconductor substrate. The measuring part measures an implantation amount of ions corresponding to an aspect ratio of the concave portion based on ions implanted from the implantation part thereinto, at a first position at which the semiconductor substrate is arranged when the ions are implanted into the implantation region or a second position close to the first position. The controller controls the implantation part to stop implantation of the ions into the measuring part when an accumulated amount of the implantation amount has reached a predetermined amount according to a target accumulation amount of the implantation region.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a first film, a conductive member and a second film. The first film is provided on the semiconductor substrate. The conductive member is provided in the first film, extends in a direction parallel to a main surface of the semiconductor substrate, and has a compressive stress. The second film is provided between the first film and the conductive member and has a tensile stress.

Abstract: According to an embodiment, a semiconductor memory device comprises a substrate, a plurality of control gate electrodes, a semiconductor layer, a charge accumulation layer, and a contact. The plurality of control gate electrodes are stacked on the substrate. The semiconductor layer has one end thereof connected to the substrate, has as its longer direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. The contact has its lower end connected to the substrate, and is adjacent to the plurality of control gate electrodes via a first insulating layer. Moreover, a boundary of a first surface that faces a lower surface of the control gate electrode and a second surface that faces a lower surface of the first insulating layer, of an upper surface of the substrate is formed continuously.

Abstract: A laminated body is disposed on a semiconductor substrate made of silicon. The laminated body includes a plurality of conductive layers and an interlayer insulating film. The interlayer insulating layer is disposed between the plurality of conductive layers. A memory cell array includes a pillar-shaped semiconductor layer and a memory gate insulating film. A peripheral area of the semiconductor layer is surrounded by the laminated body. The semiconductor layer extends with a first direction as a longitudinal direction. The memory gate insulating film is disposed between the pillar-shaped semiconductor layer and the laminated body. The memory gate insulating film includes an electric charge accumulating film. A stepped portion is disposed at an end of the laminated body. A base layer is formed under the laminated body. The base layer contains silicon and an IV group element different from the silicon.

Abstract: A semiconductor memory device according to an embodiment includes a stacked body and a pillar. The stacked body includes insulating films and electrode films. Each of the insulating films and each of the electrode films are stacked alternately. The pillar passes through the stacked body in a stacking direction of the insulating films and the electrode films. The pillar includes a semiconductor pillar disposed within the pillar extending from a top end of the pillar to a bottom end thereof, and a memory film disposed between the semiconductor pillar and one of the electrode films. Within the semiconductor pillar, a carrier density of first portions disposed in a portion opposing the insulating films is greater than a carrier density of second portions disposed in a portion opposing the electrode films.