Patents by Inventor Yasunori Tokuda
Yasunori Tokuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240192351Abstract: A vehicle occupant detection system includes: an identification unit that identifies whether or not an object in a vehicle is a person; a first detection unit that detects a velocity at which a person identified by the identification unit moves; a second detection unit that detects a situation regarding seating of the person identified by the identification unit; an output unit that outputs the situation regarding seating of the person, detected by the second detection unit; and a control unit that permits or prohibits output of the situation regarding seating of the person by the output unit on the basis of the velocity at which the person moves, detected by the first detection unit.Type: ApplicationFiled: May 13, 2021Publication date: June 13, 2024Applicant: Mitsubishi Electric CorporationInventors: Yasunori HOSHIHARA, Takumi TAKEI, Yoshikazu TOKUDA
-
Publication number: 20110316047Abstract: The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero junction field effect transistor provided with an AlxGa1-xN channel layer with a composition ratio of Al being x (0<x<1) formed on a substrate, an AlyGa1-yN barrier layer with a composition of Al being y (0<y?1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.Type: ApplicationFiled: August 29, 2011Publication date: December 29, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takuma Nanjo, Muneyoshi Suita, Yuji Abe, Toshiyuki Oishi, Yasunori Tokuda
-
Patent number: 8035130Abstract: The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero-junction field effect transistor provided with an AlxGa1-xN channel layer with a composition ratio of Al being x (0<x<1) formed on a substrate, an AlyGa1-yN barrier layer with a composition of Al being y (0<y?1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.Type: GrantFiled: March 25, 2008Date of Patent: October 11, 2011Assignee: Mitsubishi Electric CorporationInventors: Takuma Nanjo, Muneyoshi Suita, Yuji Abe, Toshiyuki Oishi, Yasunori Tokuda
-
Patent number: 7939943Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, which is an antioxidant film for preventing oxidation of the Ta film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film as an antioxidant film is formed on the entire upper surface of the Ta film which forms the p electrode, to prevent oxidation of the Ta film. This inhibits the resistance between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the low-resistance p electrode.Type: GrantFiled: November 11, 2008Date of Patent: May 10, 2011Assignee: Mitsubishi Electric CorporationInventors: Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Hiroshi Kurokawa, Kenichi Ohtsuka, Yoichiro Tarui, Yasunori Tokuda
-
Patent number: 7795738Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film is formed on the entire upper surface of the Ta film which forms part of the p electrode, and serves as an antioxidant film that prevents oxidation of the Ta film. Preventing oxidation of the Ta film, the second Pd film can reduce the resistance that may exist between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the p electrode with low resistance.Type: GrantFiled: December 4, 2008Date of Patent: September 14, 2010Assignee: Mitsubishi Electric CorporationInventors: Katsuomi Shiozawa, Kyozo Kanamoto, Hiroshi Kurokawa, Yasunori Tokuda, Kyosuke Kuramoto, Hitoshi Sakuma
-
Patent number: 7678597Abstract: A method of manufacturing a semiconductor device provides a semiconductor device with a gallium-nitride-based semiconductor structure that allows long-term stable operation without degradation in device performance. After formation of an insulation film on a surface other than on a ridge surface, an oxygen-containing gas such as O2, O3, NO, N2O, or NO2 is supplied to oxidize a p-type GaN contact layer from the surface and to thereby form an oxide film on the surface of the p-type GaN contact layer. Then, a p-type electrode that establishes contact with the p-type GaN contact layer is formed by evaporation or sputtering on the oxide film and on the insulation film. Heat treatment is subsequently performed at temperatures between 400 and 700° C. in an atmosphere containing a nitrogen-containing gas such as N2 or NH3 or an inert gas such as Ar or He.Type: GrantFiled: November 26, 2008Date of Patent: March 16, 2010Assignee: Mitsubishi Electric CorporationInventors: Kenichi Ohtsuka, Yoichiro Tarui, Yosuke Suzuki, Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Yasunori Tokuda, Tatsuo Omori
-
Publication number: 20090170304Abstract: A method of manufacturing a semiconductor device is provided, which can reduce the contact resistance of an ohmic electrode to a p-type nitride semiconductor layer and can achieve long-term stable operation. In forming, in an electrode forming step, a p-type ohmic electrode of a metal film by successive lamination of a Pd film which is a first p-type ohmic electrode and a Ta film which is a second p-type ohmic electrode on a p-type GaN contact layer, the metal film is formed to include an oxygen atom. In the presence of an oxygen atom in the metal film, then in a heat-treatment step, the p-type ohmic electrode of the metal film is heat-treated in an atmosphere that contains no oxygen atom-containing gas.Type: ApplicationFiled: December 18, 2008Publication date: July 2, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoichiro Tarui, Kenichi Ohtsuka, Yosuke Suzuki, Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Yasunori Tokuda, Tatsuo Omori
-
Publication number: 20090160054Abstract: A nitride semiconductor device is provided which reduces the contact resistance at the interface between a P-type electrode and a nitride semiconductor layer. A nitride semiconductor device includes a P-type nitride semiconductor layer and a P-type electrode formed on the P-type nitride semiconductor layer. The P-type electrode is formed by successive laminations of a metal layer of a metal having a work function of 5.1 eV or more, a Pd layer of palladium, and a Ta layer of tantalum on the P-type nitride semiconductor layer.Type: ApplicationFiled: November 13, 2008Publication date: June 25, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Yoichiro Tarui, Yasunori Tokuda
-
Publication number: 20090146308Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film is formed on the entire upper surface of the Ta film which forms part of the p electrode, and serves as an antioxidant film that prevents oxidation of the Ta film. Preventing oxidation of the Ta film, the second Pd film can reduce the resistance that may exist between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the p electrode with low resistance.Type: ApplicationFiled: December 4, 2008Publication date: June 11, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Katsuomi Shiozawa, Kyozo Kanamoto, Hiroshi Kurokawa, Yasunori Tokuda, Kyosuke Kuramoto, Hitoshi Sakuma
-
Publication number: 20090142871Abstract: A method of manufacturing a semiconductor device provides a semiconductor device with a gallium-nitride-based semiconductor structure that allows long-term stable operation without degradation in device performance. After formation of an insulation film on a surface other than on a ridge surface, an oxygen-containing gas such as O2, O3, NO, N2O, or NO2 is supplied to oxidize a p-type GaN contact layer from the surface and to thereby form an oxide film on the surface of the p-type GaN contact layer. Then, a p-type electrode that establishes contact with the p-type GaN contact layer is formed by evaporation or sputtering on the oxide film and on the insulation film. Heat treatment is subsequently performed at temperatures between 400 and 700° C. in an atmosphere containing a nitrogen-containing gas such as N2 or NH3 or an inert gas such as Ar or He.Type: ApplicationFiled: November 26, 2008Publication date: June 4, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kenichi Ohtsuka, Yoichiro Tarui, Yosuke Suzuki, Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Yasunori Tokuda, Tatsuo Omori
-
Publication number: 20090140389Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, which is an antioxidant film for preventing oxidation of the Ta film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film as an antioxidant film is formed on the entire upper surface of the Ta film which forms the p electrode, to prevent oxidation of the Ta film. This inhibits the resistance between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the low-resistance p electrode.Type: ApplicationFiled: November 11, 2008Publication date: June 4, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Hiroshi Kurokawa, Kenichi Ohtsuka, Yoichiro Tarui, Yasunori Tokuda
-
Publication number: 20080237639Abstract: The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero-junction field effect transistor provided with an AlxGa1-xN channel layer with a composition ratio of Al being x (0<x<1) formed on a substrate, an AlyGa1-yN barrier layer with a composition of Al being y (0<y?1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.Type: ApplicationFiled: March 25, 2008Publication date: October 2, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takuma NANJO, Muneyoshi Suita, Yuji Abe, Toshiyuki Oishi, Yasunori Tokuda
-
Patent number: 6635938Abstract: A polysilicon nitride film is formed to cover a polysilicon gate. By heat treatment of the silicon nitride film in an oxygen atmosphere, a silicon oxinitride film is formed. By anisotropically etching the silicon oxinitride film and the silicon nitride film, a sidewall insulating film is formed. By epitaxial growth, selective silicon films of a prescribed film thickness are formed on source and drain regions. During this period, silicon islands are not deposited on the surface of sidewall insulating film. Consequently, a semiconductor device including a transistor of a superior electrical insulation can be obtained.Type: GrantFiled: November 21, 2000Date of Patent: October 21, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takumi Nakahata, Shigemitsu Maruno, Taisuke Furukawa, Naruhisa Miura, Toshiyuki Oishi, Yasunori Tokuda
-
Patent number: 6624034Abstract: A method of producing a semiconductor device includes forming a gate electrode on a channel region on a surface of a semiconductor region of a semiconductor substrate, the channel region having a depth in the semiconductor substrate; forming a first pair of side wall spacers on opposite sides of the gate electrode; forming elevated semiconductor layers, each elevated semiconductor layer being elevated relative to the channel region, on regions outside of the pair of side wall spacers and in which source and drain regions of a first conductivity type are to be formed; removing the pair of first side wall spacers; and forming a pair of pocket injection regions of a second conductivity type by introducing, after the side wall spacers are removed, a dopant impurity producing the second conductivity type deeper in the semiconductor substrate than a region where the side wall spacers were formed, the pair of pocket injection regions respectively covering only a neighborhood of respective side surface parts of the cType: GrantFiled: June 19, 2002Date of Patent: September 23, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yuji Abe, Naruhisa Miura, Kohei Sugihara, Toshiyuki Oishi, Yasunori Tokuda
-
Patent number: 6617654Abstract: Source and drain regions include regions of an epitaxial silicon film on the surface of the substrate and regions in the substrate. The depth of junctions of the source and drain regions is identical to or shallower than the depth of junctions of extension regions. As a result, even if the thickness of the side wall layer is reduced, since the depletion layer of the extension regions with lower impurity concentration compared with the source and drain regions is predominant, the short channel effect has a smaller effect.Type: GrantFiled: September 19, 2001Date of Patent: September 9, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiyuki Oishi, Kohei Sugihara, Naruhisa Miura, Yuji Abe, Yasunori Tokuda
-
Patent number: 6566734Abstract: In making a field effect transistor, a dummy gate electrode is formed before a gate electrode is formed. Extension regions, a side wall silicon nitride film, source/drain regions, a silicon oxide film, and other elements are formed with respect to the dummy gate electrode. The dummy gate electrode is removed, and a part of the extension regions diffused into a region immediately under the dummy gate electrode is removed. The removed part is filled with silicon selection epitaxial film. Thereafter, the intended gate electrode is formed. This production method produces a field effect transistor that prevents deterioration of electrical characteristics caused by the short channel effect and parasitic resistance.Type: GrantFiled: March 16, 2001Date of Patent: May 20, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kohei Sugihara, Toshiyuki Oishi, Naruhisa Miura, Yuji Abe, Yasunori Tokuda
-
Patent number: 6518635Abstract: A major object of the present invention is to provide an improved semiconductor device so as to be able to reduce gate electric field concentration at a channel edge, suppress decrease in the threshold during MOSFET operation and reduce the leakage current. A gate insulation film is formed on a semiconductor substrate. A gate electrode is formed on the semiconductor substrate with the gate insulation film therebetween. The dielectric constant of the gate insulation film is not uniform in the surface.Type: GrantFiled: July 6, 2000Date of Patent: February 11, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuomi Shiozawa, Toshiyuki Oishi, Yuji Abe, Yasunori Tokuda
-
Publication number: 20020158292Abstract: A semiconductor device that makes it possible to restrain the increase of the junction capacitance and others while preventing the punch-through and others accompanying the scale reduction, and a production method thereof are obtained. The semiconductor device includes source and drain regions of first conductivity type disposed to sandwich a channel region, and a pair of pocket injection regions of second conductivity type that cover only a neighborhood of side surface parts of the source and drain regions on the channel region side and respectively form a junction only between the neighborhood of the side surface parts and the pocket injection regions.Type: ApplicationFiled: June 19, 2002Publication date: October 31, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Yuji Abe, Naruhisa Miura, Kohei Sugihara, Toshiyuki Oishi, Yasunori Tokuda
-
Publication number: 20020045317Abstract: Source/drain regions are formed with two regions of an epitaxial silicon film formed on the surface of the substrate and a region formed by ion implantation and thermal diffusion of impurities into the substrate, and the depth of junction of the source/drain regions is formed at a depth identical with or shallower than the depth of junction of the extension regions. As a result, even if the thickness of the side wall layer is reduced, since the depletion layer of the extension regions with lower impurity concentration compared with the source/drain regions is predominant, the short channel effect are less degraded.Type: ApplicationFiled: September 19, 2001Publication date: April 18, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Toshiyuki Oishi, Kohei Sugihara, Naruhisa Miura, Yuji Abe, Yasunori Tokuda
-
Patent number: 6373108Abstract: Source/drain diffusion regions are formed on the silicon substrate such that the source/drain diffusion regions sandwich a gate electrode from both sides on the silicon substrate. Sidewall oxide films are formed, one on each side surface of the gate electrode. Recessed portions are formed in the extension portions E beneath the sidewall oxide films. Source/drain electrodes are formed to fill the recessed portions. Thus, the sheet resistance of the respective regions including a pair of source/drain diffusion regions and source/drain electrodes is reduced, and a semiconductor device with a field-effect transistor having an improved current drivability is obtained.Type: GrantFiled: March 1, 1999Date of Patent: April 16, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Satoshi Yamakawa, Yasunori Tokuda, Takumi Nakahata, Taisuke Furukawa, Shigemitsu Maruno