Patents by Inventor Yasuo Inoue
Yasuo Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100123740Abstract: There is provided a display adjusting circuit for performing adjustment for display on a video signal to be supplied to an organic electroluminescence panel, the display adjusting circuit of the organic electroluminescence panel, comprising a linear gamma circuit where a video signal on which a predetermined gamma adjustment has been performed is supplied to be converted into a video signal with a linear gamma characteristic by cancelling the gamma adjustment of the supplied video signal and to be output, an adjusting circuit to which the video signal output from the linear gamma circuit is supplied, and a panel gamma circuit where the video signal output from the adjusting circuit is supplied to be converted into a video signal with a gamma characteristic corresponding to a gamma characteristic of the organic electroluminescence panel and to be output, the adjusting circuit including a detecting unit for detecting a driving state or a driving history of the organic electroluminescence panel from the suppliedType: ApplicationFiled: April 24, 2008Publication date: May 20, 2010Applicant: SONY CORPORATIONInventors: Yasuo Inoue, Masahiro Ito
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Publication number: 20100118062Abstract: There is provided a display device including a display unit having pixels, each of which includes a luminescence element for individually emitting light depending on a current amount and a pixel circuit for controlling a current applied to the luminescence element according to a picture signal, scan lines which supply a selection signal for selecting the pixels to emit light to the pixels in a predetermined scanning cycle, and data lines which supply the picture signal to the pixels, the pixels, the scan lines, and the data lines arranged in a matrix pattern, the display device including: a luminescence amount detector for inputting a picture signal with a linear characteristic to detect a luminescence amount from the picture signal; a luminescence time calculator for calculating a luminescence time for the luminescence element based on the luminescence amount detected by the luminescence amount detector; a luminescence time recorder for recording the calculated luminescence time; a luminance acquirer for acqType: ApplicationFiled: May 15, 2008Publication date: May 13, 2010Applicant: Sony CorporationInventors: Hideto Mori, Ken Kikuchi, Yasuo Inoue, Takeya Meguro, Hidehiko Shidara, Masahiro Ito, Toyo Osumi
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Patent number: 7702819Abstract: A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.Type: GrantFiled: December 17, 2007Date of Patent: April 20, 2010Assignee: Hitachi, Ltd.Inventor: Yasuo Inoue
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Patent number: 7702823Abstract: This invention enables a disk subsystem that employs the FC-AL connection to grasp the operation status of each disk drive, quickly locate a disk drive that has failed, and promptly carry out blocking processing. In a disk subsystem including plural drive enclosures which store disk drives, and a disk controller which controls transfer of data stored in the disk drives between the drive enclosures and a host computer. The drive enclosures each comprise a backend switch which is connected to the disk drives and to the disk controller, the backend switch comprises a status monitoring port through which operation status of switch ports of the backend switch is outputted, and the disk controller monitors a fault of the switch ports through the status monitoring port.Type: GrantFiled: November 4, 2004Date of Patent: April 20, 2010Assignee: Hitachi, Ltd.Inventors: Mutsumi Hosoya, Akira Fujibayashi, Shuji Nakamura, Yasuo Inoue
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Patent number: 7644263Abstract: A PLD is interposed on the communication route between a microprocessor (hereinbelow called MP) and boot memories. The boot memories store MP start-up data needed to start up the MP and start-up protection code constituting protection code for the MP start-up data. The PLD reads the MP start-up data and the start-up protection code thereof from the boot memories, performs, in hardware fashion, a check of the validity of the MP start-up data using this start-up protection code and, if a negative check result is obtained, resets the MP and if a positive check result is obtained, inputs the start-up data that is thus read to the MP.Type: GrantFiled: October 17, 2007Date of Patent: January 5, 2010Assignee: Hitachi, Ltd.Inventors: Masanori Fujii, Yasuo Inoue, Nobuyuki Minowa
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Publication number: 20090245143Abstract: Conference system includes a conference status recording unit recording an identifier of a conference using allocated resources and a usefulness value indicating the degree of usefulness of the conference. A request accepting unit accepts a conference start request from a user. A conference opening unit instructs a multipoint connection apparatus to secure resources for use in the requested conference and records an identifier of the conference to be started and an initial usefulness value of the conference in the conference status recording unit. A resource releasing unit, when there are no available resources necessary for the new conference accepted, selects another open conference, of which resources may be released, based on the usefulness value of the other open conference recorded in the conference status recording unit, and instructs the multipoint connection apparatus to release the resources allocated to the selected open conference.Type: ApplicationFiled: March 26, 2009Publication date: October 1, 2009Applicant: FUJITSU LIMITEDInventors: Mari Hamachi, Yasuo Inoue, Masatoshi Kaneko
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Patent number: 7588835Abstract: A method of treating the surface of copper is provided to ensure adhesive strength between the surface of copper and an insulating layer without forming irregularities exceeding 1 ?m on the surface of copper and to improve insulation reliability between wirings. A copper whose surface is treated by the above surface treating method is also provided. The method of treating the surface of copper comprises the surface of copper comprising the steps of: forming a metal nobler than copper discretely on the surface of copper; and subsequently oxidizing the surface of copper by using an alkaline solution containing an oxidant.Type: GrantFiled: March 10, 2006Date of Patent: September 15, 2009Assignee: Hitachi Chemical Company, Ltd.Inventors: Tomoaki Yamashita, Yasuo Inoue, Masaharu Matsuura, Toyoki Ito, Akira Shimizu, Fumio Inoue, Akishi Nakaso
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Publication number: 20090135304Abstract: There is provided a display device equipped with a display unit, the display device including a receiving part for receiving a difference signal of a plurality of channels including an image signal and content identification information inserted in a blanking period and outputting the image signal and the content identification information; a light emission amount regulation part for setting a reference duty according to image information of the image signal; an adjustment part for adjusting so that an actual duty is within a predetermined range based on the reference duty and an adjustment signal and adjusting a gain of the image signal so that a light emission amount defined by the actual duty and the gain of the image signal becomes the same as the light emission amount defined by the reference duty; and an adjustment signal generation part for generating the adjustment signal based on the content identification information.Type: ApplicationFiled: November 14, 2008Publication date: May 28, 2009Inventors: Yasuo INOUE, Toshihide HAYASHI, Masayuki TSUMURA, Koki TSUMORI, Katsuhiro SHIMIZU, Ban KAWAMURA, Ryuichi OKUMURA
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Publication number: 20090077272Abstract: A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and a switch adapter for configuring an inner network by interconnecting the channel adapter, memory adapter and processor adapter, wherein the channel adapter, memory adapter, processor adapter and switch adapter each include a DMA controller for performing a communication protocol control of the inner network; and packet multiplex communication is performed among the DMA controllers provided in the adapters. The disk controller can realize a high transfer efficiency and a low cost while retaining a high reliability.Type: ApplicationFiled: November 12, 2008Publication date: March 19, 2009Inventors: Mutsumi Hosoya, Naoki Watanabe, Shuji Nakamura, Yasuo Inoue, Kazuhisa Fujimoto, Kentaro Shimada
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Patent number: 7469307Abstract: A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and a switch adapter for configuring an inner network by interconnecting the channel adapter, memory adapter and processor adapter, wherein the channel adapter, memory adapter, processor adapter and switch adapter each include a DMA controller for performing a communication protocol control of the inner network; and packet multiplex communication is performed among the DMA controllers provided in the adapters. The disk controller can realize a high transfer efficiency and a low cost while retaining a high reliability.Type: GrantFiled: January 12, 2007Date of Patent: December 23, 2008Assignee: Hitachi, Ltd.Inventors: Mutsumi Hosoya, Naoki Watanabe, Shuji Nakamura, Yasuo Inoue, Kazuhisa Fujimoto
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Patent number: 7467238Abstract: A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and a switch adapter for configuring an inner network by interconnecting the channel adapter, memory adapter and processor adapter, wherein the channel adapter, memory adapter, processor adapter and switch adapter each include a DMA controller for performing a communication protocol control of the inner network; and packet multiplex communication is performed among the DMA controllers provided in the adapters. The disk controller can realize a high transfer efficiency and a low cost while retaining a high reliability. A storage system includes an interface unit having an interface with a server or hard drives, a memory unit, a processor unit, and an interconnection.Type: GrantFiled: October 11, 2005Date of Patent: December 16, 2008Assignee: Hitachi, Ltd.Inventors: Mutsumi Hosoya, Naoki Watanabe, Shuji Nakamura, Yasuo Inoue, Kazuhisa Fujimoto, Kentaro Shimada
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Publication number: 20080291136Abstract: There is provided a display device provided with a display portion, in which pixels having a light-emitting element for self-light-emitting, and a pixel circuit for controlling a current applied to a light-emitting element according to a voltage signal are arranged in a matrix, provided with an average luminance calculation portion calculating an average of luminance of an input video signal, and a light-emitting time setting portion setting a real duty defined every one frame by which light-emitting time for light emitting of the light-emitting element according to a calculated average luminance, wherein the light-emitting time setting portion sets the real duty in such a way that a light-emitting amount defined by a standard duty set beforehand and a maximum luminance among those of a video signal, and a light-emitting amount defined by a real duty to be set and an average luminance become the same as each other.Type: ApplicationFiled: May 15, 2008Publication date: November 27, 2008Applicant: SONY CORPORATIONInventors: Yasuo Inoue, Yoshihiro Kosugi, Ken Kikuchi, Takeya Meguro, Hideto Mori, Toyo Osumi
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Publication number: 20080284702Abstract: A display device includes: an average value calculating section which inputs video signals having linear property and calculates an average value of levels of the video signals in each pixel; an average value memory section which sequentially stores the average values calculated by the average value calculating section; a still image determining section which determines whether a still image is displayed on a present screen based on a difference between the average value stored in the average value memory section and a last average value; a coefficient calculating section which, when the determination is made that a still image is displayed on the present screen as a result of the determination in the still image determining section, calculates coefficients for lowering luminance of an image displayed on the display device; and a coefficient multiplying section which multiplies the video signals by the coefficients calculated by the coefficient calculating section.Type: ApplicationFiled: May 14, 2008Publication date: November 20, 2008Applicant: SONY CORPORATIONInventors: Hidehiko Shidara, Ken Kikuchi, Yasuo Inoue, Masahiro Ito, Hideto Mori
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Publication number: 20080284767Abstract: A display device includes: a light emission amount detecting section which inputs video signals having linear property and detects an amount of light emission from the video signals; a light emitting time calculating section which calculates light emitting time of the light emitting elements based on the amount of light emission detected by the light emission amount detecting section; a light emitting time recording section which records the calculated light emitting time; a luminance acquiring section which, acquires luminance information of the light emitting elements using the light emitting time recorded in the light emitting time recording section; a coefficient calculating section which calculates coefficients by which the video signals are multiplied based on the luminance information acquired by the luminance acquiring section; and a coefficient multiplying section which multiplies the video signals by the coefficients calculated by the coefficient calculating section.Type: ApplicationFiled: May 15, 2008Publication date: November 20, 2008Applicant: SONY CORPORATIONInventors: Hideto Mori, Ken Kikuchi, Yasuo Inoue, Takeya Meguro, Hidehiko Shidara, Masahiro Ito, Toyo Osumi
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Publication number: 20080278421Abstract: A correction method for correcting uneven light emission of an organic EL panel, the correction method includes the steps of: supplying a predetermined signal to the organic EL panel to detect the brightness of the panel at horizontal and vertical scan positions; forming, based on a detection output thereof, correction data adapted to correct uneven brightness of the organic EL panel at a horizontal or vertical display position of the panel; storing the correction data in a memory; and reading the correction data from the memory during viewing to correct the level of a video signal supplied to the organic EL panel.Type: ApplicationFiled: May 6, 2008Publication date: November 13, 2008Applicant: SONY CORPORATIONInventors: Yasuo Inoue, Ken Kikuchi, Takeya Meguro, Hideto Mori
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Publication number: 20080266332Abstract: A display correction circuit of an organic EL panel for correcting, for display purposes, a video signal supplied to an organic EL panel, the display correction circuit includes: a linear gamma circuit supplied with a video signal which has been subjected to a predetermined gamma correction, the linear gamma circuit adapted to cancel the gamma correction of the video signal to convert the signal into a video signal having a linear gamma characteristic and adapted to output the resultant signal; a correction circuit supplied with the video signal from the linear gamma circuit; and a panel gamma circuit supplied with the video signal from the correction circuit, the panel gamma circuit adapted to convert the video signal into a video signal having a gamma characteristic associated with the gamma characteristic of the organic EL panel and adapted to output the resultant signal.Type: ApplicationFiled: April 24, 2008Publication date: October 30, 2008Applicant: SONY CORPORATIONInventors: Yasuo Inoue, Masahiro Ito
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Patent number: 7444467Abstract: A storage system, coupled to a host computer, including at least one controller receiving data from the host computer, and a plurality of memory units connected to the controller. The controller generates parity data and sends the data and the parity data to the memory units. The memory units include a semiconductor memory device which stores the data and the parity data permanently.Type: GrantFiled: June 29, 2006Date of Patent: October 28, 2008Assignee: Hitachi, Ltd.Inventors: Tatuya Ninomiya, Hidefumi Masuzaki, Hiroyuki Kurosawa, Naoya Takahashi, Yasuo Inoue, Hidehiko Iwasaki, Masayuki Hoshino, Soichi Isono
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Publication number: 20080170494Abstract: A communication apparatus communicably connects a network of a plurality of apparatuses and a data relay apparatus to another network of the same manner as that of the network by detecting a failure occurring in the network, and determining a detour to assure communication between an apparatus connected to a network disconnected due to the failure detected and the other network. A tunneling is established serving as a virtual direct communication circuit to the determined detour.Type: ApplicationFiled: January 8, 2008Publication date: July 17, 2008Applicant: Fujitsu LimitedInventors: Tooru ENOKI, Yasuo INOUE, Shinichi HAYASHI
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Publication number: 20080133788Abstract: A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.Type: ApplicationFiled: December 17, 2007Publication date: June 5, 2008Inventor: Yasuo Inoue
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Publication number: 20080096046Abstract: A method of treating the surface of copper is provided to ensure adhesive strength between the surface of copper and an insulating layer without forming irregularities exceeding 1 ?m on the surface of copper and to improve insulation reliability between wirings. A copper whose surface is treated by the above surface treating method is also provided. The method of treating the surface of copper comprises the surface of copper comprising the steps of: forming a metal nobler than copper discretely on the surface of copper; and subsequently oxidizing the surface of copper by using an alkaline solution containing an oxidant.Type: ApplicationFiled: March 10, 2006Publication date: April 24, 2008Inventors: Tomoaki Yamashita, Yasuo Inoue, Masaharu Matsuura, Toyoki Ito, Akira Shimizu, Fumio Inoue, Akishi Nakaso