Abstract: A floor plan and a cell layout in each of a plurality of blocks are designed. A clock tree is generated in such a manner that the clock skew in each lower level block is minimum. Placement position of a root clock driver and information about an area where the cells can be placed are given to the upper level block. An average delay value of delay values from the root clock driver to a distal buffer is obtained for each block. A flock tree is generated based on these information in such a manner that the clock skew between the higher level block is minimum. If a buffer is newly generated, then its placement position is adjusted based on the cell layout of the lower level block. Wire is distributed in the lower and then in the higher level blocks.

Abstract: A method conducts logic simulation in an integrated circuit device, in which a macro containing logic circuits formed therein is included in a chip including a plurality of cells. The method determines a first delay parameter relating to an input terminal of an internal cell of the macro connected to the input terminal of the macro, and a second delay parameter relating to an output terminal of an internal cell of the macro connected to the output terminal of the macro. The method then determines delay time data for a whole logic circuit including the plurality of cells and the macro, in accordance with delay parameters determined for the macro, in which the first delay parameter is taken as an input terminal delay parameter and the second delay parameter is taken as an output terminal delay parameter; delay parameters determined for the plurality of cells; and connection data for the whole logic circuit.

Abstract: The present invention relates to a method for producing a compound of the formula: wherein R1 is an optionally substituted hydrocarbon group; R2 is H or an optionally substituted hydrocarbon group; and Q is an optionally substituted heterocyclic group, or a salt thereof which comprises subjecting a compound of the formula: wherein R1 has the same meaning as defined above, or a salt thereof to a nitration reaction (a), and further subjecting the resulting mixture without isolating/purifying the resulting compound of the formula: wherein R1 has the same meaning as defined above, or a salt thereof to a reaction (b) with a compound of the formula: Q—CH2—NH—R2  [III] wherein each symbol has the same meaning as defined above, or a salt thereof.

Abstract: A process for producing the compound [I] or a salt thereof having excellent pesticidal activity as shown in the following schema.

Abstract: A process for producing 2-halogenoallyl isothiocyanate ?I! represented by the formula: ##STR1## wherein X.sup.1 is a halogen atom, is disclosed. The process comprises reacting a compound represented by the formula: ##STR2## wherein X.sup.1 is a halogen atom and X.sup.2 is a leaving group, with a thiocyanate represented by the formula;M(SCN)nwherein M is a metal or an ammonium group and n is a valence number of M, in the presence of water under heating. According to the process for producing of the present invention, 2-halogenoallyl isothiocyanata ?I!, which has an insecticidal effect as such and is useful as an intermediate for a medicine, an agricultural chemical and the like, can be produced on an industrially large scale in a good yield.