Patents by Inventor Yasuo Kitayama
Yasuo Kitayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10483983Abstract: A clock generating circuit includes a dividing unit and a distribution unit. The dividing unit divides a reference clock to generate a divided clock, and the divided clock has a frequency of 1/N times of a frequency of the reference clock, where N is an integer of two or more. The distribution unit distributes the reference clock to a first route and a second route, the first route includes an output terminal that outputs a clock with a frequency identical to the frequency of the reference clock, and the second route includes the dividing unit. The dividing unit includes one or more amplifiers, one or more dividing circuits, and a correction circuit. The correction circuit is disposed between the amplifier and the dividing circuit, and the correction circuit corrects a level of an input clock input to the dividing circuit.Type: GrantFiled: August 23, 2017Date of Patent: November 19, 2019Assignee: NIHON DEMPA KOGYO CO., LTD.Inventors: Tomoya Yorita, Shoichi Tsuchiya, Yasuo Kitayama
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Publication number: 20180076818Abstract: A clock generating circuit includes a dividing unit and a distribution unit. The dividing unit divides a reference clock to generate a divided clock, and the divided clock has a frequency of 1/N times of a frequency of the reference clock, where N is an integer of two or more. The distribution unit distributes the reference clock to a first route and a second route, the first route includes an output terminal that outputs a clock with a frequency identical to the frequency of the reference clock, and the second route includes the dividing unit. The dividing unit includes one or more amplifiers, one or more dividing circuits, and a correction circuit. The correction circuit is disposed between the amplifier and the dividing circuit, and the correction circuit corrects a level of an input clock input to the dividing circuit.Type: ApplicationFiled: August 23, 2017Publication date: March 15, 2018Applicant: NIHON DEMPA KOGYO CO., LTD.Inventors: Tomoya YORITA, Shoichi TSUCHIYA, Yasuo KITAYAMA
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Patent number: 9300250Abstract: To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a digital/analog converter in accordance with a detection voltage, a technology with which a spurious due to a change in an output of the digital/analog converter can be suppressed. A low-pass filter is provided between an output side of a digital/analog converter and a variable attenuator to cut a frequency component corresponding to an overshoot generated when an output of the digital/analog converter is changed.Type: GrantFiled: November 18, 2013Date of Patent: March 29, 2016Assignee: NIHON DEMPA KOGYO CO., LTD.Inventors: Yasuo Kitayama, Hiroyuki Demura, Naoki Onishi
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Publication number: 20140077844Abstract: To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a digital/analog converter in accordance with a detection voltage, a technology with which a spurious due to a change in an output of the digital/analog converter can be suppressed. A low-pass filter is provided between an output side of a digital/analog converter and a variable attenuator to cut a frequency component corresponding to an overshoot generated when an output of the digital/analog converter is changed.Type: ApplicationFiled: November 18, 2013Publication date: March 20, 2014Applicant: NIHON DEMPA KOGYO CO., LTD.Inventors: Yasuo Kitayama, Hiroyuki Demura, Naoki Onishi
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Patent number: 8633735Abstract: To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a digital/analog converter in accordance with a detection voltage, a technology with which a spurious due to a change in an output of the digital/analog converter can be suppressed. A low-pass filter is provided between an output side of a digital/analog converter and a variable attenuator to cut a frequency component corresponding to an overshoot generated when an output of the digital/analog converter is changed.Type: GrantFiled: September 15, 2011Date of Patent: January 21, 2014Assignee: Nihon Dempa Kogyo Co., Ltd.Inventors: Yasuo Kitayama, Hiroyuki Demura, Naoki Onishi
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Publication number: 20120105110Abstract: To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a digital/analog converter in accordance with a detection voltage, a technology with which a spurious due to a change in an output of the digital/analog converter can be suppressed. A low-pass filter is provided between an output side of a digital/analog converter and a variable attenuator to cut a frequency component corresponding to an overshoot generated when an output of the digital/analog converter is changed.Type: ApplicationFiled: September 15, 2011Publication date: May 3, 2012Applicant: NIHON DEMPA KOGYO CO., LTD.Inventors: Yasuo Kitayama, Hiroyuki Demura, Naoki Onishi
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Patent number: 8149069Abstract: A low noise voltage-controlled oscillating circuit which can remove a power source noise to improve low frequency noise characteristics is disclosed. A capacitor C11 is provided between a base of a driving transistor Q1 and GND, whereby a low frequency noise input into the base can be removed. As the driving transistor Q1, a transistor having a low hFE is used, whereby the low frequency noise input from a power source can be removed. A coil L3 is provided on the emitter side of an oscillating transistor Q2, whereby broadband frequency characteristics can be obtained to improve phase noise frequency characteristics. On the emitter side of the oscillating transistor Q2, a resonance frequency in a resonant circuit having a capacitor C7 and the coil L3 is set near the center of a VCO oscillation frequency band, whereby it is possible to obtain the oscillation frequency which is not easily influenced by the noise.Type: GrantFiled: June 8, 2010Date of Patent: April 3, 2012Assignee: Nihon Dempa Kogyo Co., LtdInventors: Yasuo Kitayama, Hiroyuki Demura
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Patent number: 7893774Abstract: A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.Type: GrantFiled: June 29, 2010Date of Patent: February 22, 2011Assignee: Nihon Dempa Kogyo Co., LtdInventors: Yasuo Kitayama, Hiroki Kimura, Naoki Onishi, Nobuo Tsukamoto
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Publication number: 20100308929Abstract: A low noise voltage-controlled oscillating circuit which can remove a power source noise to improve low frequency noise characteristics is disclosed. A capacitor C11 is provided between a base of a driving transistor Q1 and GND, whereby a low frequency noise input into the base can be removed. As the driving transistor Q1, a transistor having a low hFE is used, whereby the low frequency noise input from a power source can be removed. A coil L3 is provided on the emitter side of an oscillating transistor Q2, whereby broadband frequency characteristics can be obtained to improve phase noise frequency characteristics. On the emitter side of the oscillating transistor Q2, a resonance frequency in a resonant circuit having a capacitor C7 and the coil L3 is set near the center of a VCO oscillation frequency band, whereby it is possible to obtain the oscillation frequency which is not easily influenced by the noise.Type: ApplicationFiled: June 8, 2010Publication date: December 9, 2010Inventors: Yasuo Kitayama, Hiroyuki Demura
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Patent number: 7821344Abstract: A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.Type: GrantFiled: July 22, 2008Date of Patent: October 26, 2010Assignee: Nihon Dempa Kogyo Co., LtdInventors: Yasuo Kitayama, Hiroki Kimura, Naoki Onishi, Nobuo Tsukamoto
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Publication number: 20100264962Abstract: A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.Type: ApplicationFiled: June 29, 2010Publication date: October 21, 2010Inventors: Yasuo KITAYAMA, Hiroki Kimura, Naoki Onishi, Nobuo Tsukamoto
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Patent number: 7791416Abstract: A PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band is provided. The PLL circuit comprises, at the succeeding stage, a first register for storing a first parameter for controlling the loop gain, a first multiplier for multiplying the output of the phase comparator by a first parameter, a second register for storing a second parameter for controlling the response characteristic, a second multiplier for multiplying the output of the first multiplier by a second parameter, and a CPU for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved.Type: GrantFiled: August 11, 2008Date of Patent: September 7, 2010Assignee: Nihon Dempa Kogyo Co., Ltd.Inventors: Hiroki Kimura, Tsukasa Kobata, Yasuo Kitayama, Naoki Onishi
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Patent number: 7656208Abstract: A digitally controlled PLL oscillation circuit has a VCO, a frequency divider, a reference oscillation circuit, an A/D converter, a phase comparator, a digital filter, a D/A converter, and an analog filter. A reference signal supplied from the reference oscillation circuit is output through a narrow-band crystal filter (MCF) to the A/D converter to cancel noise, jitter and a spurious wave included in the reference signal, making it possible to prevent the phase noise characteristic and spurious characteristic of a VCO output from being degraded.Type: GrantFiled: June 19, 2007Date of Patent: February 2, 2010Assignee: Nihon Dempa Kogyo., Ltd.Inventors: Hiroki Kimura, Tsukasa Kobata, Yasuo Kitayama, Naoki Onishi
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Publication number: 20090039973Abstract: A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.Type: ApplicationFiled: July 22, 2008Publication date: February 12, 2009Inventors: Yasuo Kitayama, Hiroki Kimura, Naoki Onishi, Nobuo Tsukamoto
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Publication number: 20090021312Abstract: It has been difficult that conventional PLL circuits have a suppression characteristic of suppressing the phase noise which is free of variation due to temperature and individual difference and stable in a wide frequency band. The present invention provides a PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band.Type: ApplicationFiled: August 11, 2008Publication date: January 22, 2009Inventors: Hiroki Kimura, Tsukasa Kobata, Yasuo Kitayama, Naoki Onishi
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Publication number: 20080042708Abstract: A digitally controlled PLL oscillation circuit has a VCO, a frequency divider, a reference oscillation circuit, an A/D converter, a phase comparator, a digital filter, a D/A converter, and an analog filter. A reference signal supplied from the reference oscillation circuit is output through a narrow-band crystal filter (MCF) to the A/D converter to cancel noise, jitter and a spurious wave included in the reference signal, making it possible to prevent the phase noise characteristic and spurious characteristic of a VCO output from being degraded.Type: ApplicationFiled: June 19, 2007Publication date: February 21, 2008Inventors: Hiroki Kimura, Tsukasa Kobata, Yasuo Kitayama, Naoki Onishi