Patents by Inventor Yasuo Nakatani

Yasuo Nakatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11548804
    Abstract: There is provided a method of processing an oxygen-containing workpiece. The method of processing an oxygen-containing workpiece includes controlling a fluorine concentration in the oxygen-containing workpiece based on at least one of a kind of a fluorine-containing processing gas, a processing temperature and a processing pressure used for processing the oxygen-containing workpiece.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: January 10, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Reiko Sasahara, Yasuo Nakatani, Keiko Hada
  • Publication number: 20220336238
    Abstract: A heating/cooling device includes: a chamber; a plurality of substrate holders provided inside the chamber to support substrates; a plurality of LED light sources provided outside the chamber to irradiate the substrates held on the substrate holders with LED light having a wavelength that heats the substrates; a plurality of transmission windows provided between the plurality of substrate holders and the plurality of LED light sources to transmit the LED light radiated from the LED light sources; and a plurality of gas distribution parts provided inside the chamber to distribute and supply a cooling gas to the substrates held on the substrate holders.
    Type: Application
    Filed: August 6, 2020
    Publication date: October 20, 2022
    Inventors: Shosuke ENDO, Yohei MIDORIKAWA, Yohei NAKAGOMI, Yoshihiro KOBAYASHI, Yasuo NAKATANI, Susumu SAITO, Chanseong AHN, Yuta TAKAHASHI, Takahiro KIJIMA
  • Publication number: 20200048134
    Abstract: There is provided a method of processing an oxygen-containing workpiece. The method of processing an oxygen-containing workpiece includes controlling a fluorine concentration in the oxygen-containing workpiece based on at least one of a kind of a fluorine-containing processing gas, a processing temperature and a processing pressure used for processing the oxygen-containing workpiece.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 13, 2020
    Inventors: Reiko SASAHARA, Yasuo NAKATANI, Keiko HADA
  • Patent number: 6781188
    Abstract: Disclosed is a nonvolatile semiconductor memory device in which a disturbance phenomenon can be prevented. A nonvolatile semiconductor memory device has a semiconductor substrate, and a floating gate electrode formed on the semiconductor substrate via a gate insulating film. The floating gate electrode includes a lower conductive layer formed on the gate insulating film and having a first width W1 in a channel width direction, and an upper conductive layer formed on the lower conductive layer and having a second width W2 wider than the first width W1 in the channel width direction.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: August 24, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Yasuo Nakatani
  • Publication number: 20030098485
    Abstract: Disclosed is a nonvolatile semiconductor memory device in which a disturbance phenomenon can be prevented. A nonvolatile semiconductor memory device has a semiconductor substrate, and a floating gate electrode formed on the semiconductor substrate via a gate insulating film. The floating gate electrode includes a lower conductive layer formed on the gate insulating film and having a first width W1 in a channel width direction, and an upper conductive layer formed on the lower conductive layer and having a second width W2 wider than the first width W1 in the channel width direction.
    Type: Application
    Filed: May 24, 2002
    Publication date: May 29, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yasuo Nakatani
  • Patent number: 6446641
    Abstract: There is described a method of manufacturing a semiconductor device for accurately and anisotropically etching desired locations on a semiconductor wafer at high selectivity. A polysilicon layer which is to act as a floating gate is embedded in the surface of an oxide film insulating layer. Control gates are formed in a direction orthogonal to the polysilicon layer. Exposed portions of the polysilicon layer are subjected to dry-etching, thereby forming a floating gate. Residues remaining in the channels formed in the oxide film insulating layer are removed by means of wet etching.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: September 10, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yasuo Nakatani
  • Publication number: 20020001959
    Abstract: There is described a method of manufacturing a semiconductor device for accurately and anisotropically etching desired locations on a semiconductor wafer at high selectivity. A polysilicon layer which is to act as a floating gate is embedded in the surface of an oxide film insulating layer. Control gates are formed in a direction orthogonal to the polysilicon layer. Exposed portions of the polysilicon layer are subjected to dry-etching, thereby forming a floating gate. Residues remaining in the channels formed in the oxide film insulating layer are removed by means of wet etching.
    Type: Application
    Filed: December 19, 2000
    Publication date: January 3, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yasuo Nakatani
  • Patent number: 6188099
    Abstract: A storage node to be a lower electrode of a capacitor is electrically connected to a polysilicon columnar conductive body filling a contact hole with a second polysilicon film therebetween. The second polysilicon film covers the inside of an opening portion formed in the first polysilicon film. The polysilicon film columnar conductive body is electrically connected to a source/drain region of an MOS transistor at a contact. Thus, a semiconductor device with good electrical connection between the capacitor and the transistor may be provided.
    Type: Grant
    Filed: May 14, 1997
    Date of Patent: February 13, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yasuo Nakatani