Patents by Inventor Yasushi Amamiya

Yasushi Amamiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6087684
    Abstract: A heterojunction bipolar transistor (HBT) has shortened electron transport time through collector region over wide range of biased conditions. The HBT is expected to exhibit enhanced high frequency characteristics. In operation under biased condition, a portion of an n-GaAs collector layer makes a depletion region. A p-GaAs base contact layer is in contact with side surface of the depletion region. Even if the collector layer remains in the n-type, the contour of band potential in conduction band of the collector depletion region is adjusted to a desired one by controlling electric potential of the base contact layer. As a result, the band potential with smooth slope is created in the collector depletion region, shortening transport time through the collector layer. The intrinsic portion of the collector layer is of the n-type so that occurrence of Kirk effect is suppressed, ensuring enhanced high frequency characteristics.
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: July 11, 2000
    Assignee: NEC Corporation
    Inventor: Yasushi Amamiya
  • Patent number: 6037616
    Abstract: In a bipolar transistor including a semi-insulating substrate, a collector layer formed on the semi-insulating substrate and a base layer formed on the collector layer, a base contact layer is in contact; with a part of a lower surface of the base layer.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: March 14, 2000
    Assignee: NEC Corporation
    Inventor: Yasushi Amamiya