Abstract: A memory control device of the present invention controls a memory that includes multiple bank groups each including multiple banks. The memory control device includes a request buffer configured to store memory requests to be issued to the banks, a bank busy manager configured to manage busy states of the banks, a bank group checker configured to, for each of the banks, manage the number of banks in not-busy state of the banks in each of the bank groups, a bank group determination unit configured to determine a bank group to which a memory request is issued, on the basis of the numbers of the banks in not-busy state in the respective bank groups, and a request issuer configured to issue the memory request in the request buffer to a bank in the determined bank group.

Abstract: A memory control device of the present invention controls a memory that includes multiple bank groups each including multiple banks. The memory control device includes a request buffer configured to store memory requests to be issued to the banks, a bank busy manager configured to manage busy states of the banks, a bank group checker configured to, for each of the banks, manage the number of banks in not-busy state of the banks in each of the bank groups, a bank group determination unit configured to determine a bank group to which a memory request is issued, on the basis of the numbers of the banks in not-busy state in the respective bank groups, and a request issuer configured to issue the memory request in the request buffer to a bank in the determined bank group.

Abstract: To enable moving and copying structured data as block data at high speed, and tracing the moved or copied structured data at high speed. A data processing apparatus that processes structured data including a pointer includes a processing unit configured to process the structured data that uses as the pointer a relative address whose origin is the address of a word in which the pointer is stored.

Abstract: A data transfer system includes: a plurality of processors; and a plurality of data transfer units that executes a data transfer from one processor to another processor via a plurality of input ports and a plurality of output ports. The data transfer unit includes: an arbitration unit that executes arbitration of conflicting data sent to a same next destination; and a strength information notification unit that sends strength information indicating a number of conflicts of the arbitrated conflicting data to the next destination. The arbitration unit decides a selection ratio, which is a ratio of selecting each of the input ports and receiving the conflicting data from the selected input port, according to a ratio between the input ports in relation to a magnitude of the number of conflicts indicated by the strength information received from each of the input ports.

Abstract: To enable moving and copying structured data as block data at high speed, and tracing the moved or copied structured data at high speed. A data processing apparatus that processes structured data including a pointer includes a processing unit configured to process the structured data that uses as the pointer a relative address whose origin is the address of a word in which the pointer is stored.

Abstract: A cache memory comprises a data array that stores a cashed block; a first address array that stores an address of the cached block; a second address array that stores an address of a first block to be removed from the data array when a cache miss occurs; and a control unit that transmits to a processor the first block stored in the data array as a cache hit block, when the address stored in the second address array results in a cache hit during a period before a second block which has caused the cache miss is read from a memory and written into the data array.

Abstract: A communication method is provided to reduce an overhead of inter-processor synchronization for a communication phase in collective communication and to speed up the collective communication. Each of processors in a parallel computer start a previous process before a collective communication phase in which communications are performed at a same time among the processors through a inter-processor network. Each processor executes a synchronization command in advance at a time when a portion of the previous process for a predetermined time t is left. The inter-processor synchronization control section transmits a synchronization completion notice to each processor, if a synchronization condition is met. For the period, each processor executes the previous process in parallel. Then, the plurality of processors enter the collective communication phase.

Abstract: The number of ways of address arrays (102, 103, and 104) is made greater than the number of ways of data arrays (105 and 106). At the time of a mishit, a request is issued to read from memory (3) block data of the address of the mishit and the address in an address entry of an available address array. At this time, the address entry of an address array and the data entry of a data array that correspond to block data to be replaced are kept valid until the arrival of the block data corresponding to the read request in cache memory system (1) from memory (3). Therefore, access from CPU (2) to block data to be replaced can be handled as a cache hit when access occurs before the block data corresponding to the read request arrive in the cache memory system (1) from memory 3.

Abstract: A data transfer system includes: a plurality of processors; and a plurality of data transfer units that executes a data transfer from one processor to other processor via a plurality of input ports and a plurality of output ports. The data transfer unit includes: an arbitration unit that executes arbitration of conflicting data sent to a same next destination; and a strength information notification unit that sends strength information indicating a number of conflicts of the arbitrated conflicting data to the next destination. The arbitration unit decides a selection ratio, which is a ratio of selecting each of the input ports and receiving the conflicting data from the selected input port, according to a ratio between the input ports in relation to magnitude of the number of conflicts indicated by the strength information received from each of the input ports.

Abstract: A cache memory comprises a data array that stores a cashed block; a first address array that stores an address of the cached block; a second address array that stores an address of a first block to be removed from the data array when a cache miss occurs; and a control unit that transmits to a processor the first block stored in the data array as a cache hit block, when the address stored in the second address array results in a cache hit during a period before a second block which has caused the cache miss is read from a memory and written into the data array.

Abstract: A communication method is provided to reduce an overhead of inter-processor synchronization for a communication phase in collective communication and to speed up the collective communication. Each of processors in a parallel computer start a previous process before a collective communication phase in which communications are performed at a same time among the processors through a inter-processor network. Each processor executes a synchronization command in advance at a time when a portion of the previous process for a predetermined time t is left. The inter-processor synchronization control section transmits a synchronization completion notice to each processor, if a synchronization condition is met. For the period, each processor executes the previous process in parallel. Then, the plurality of processors enter the collective communication phase.

Abstract: An inter-processor communication system includes processors and a transfer device that, upon receiving a multicast packet from any of the processors, transfers the packet to processors designated in the packet as destinations among the processors. Each processor includes: a memory unit; a holding unit which holds position information indicating a reference position in the memory unit; a transmitting unit which transmits to the transfer device a multicast packet representing data and an adjustment value indicating an area for writing data that was set for use by its own processor by using the reference position; and a receiving unit which, upon receiving a multicast packet that has been transmitted by way of the transfer device, determines a write position in the memory unit based on the adjustment value in the packet and the position information and stores the data in the packet in that write position.

Abstract: An apparatus includes a queue element which stores a plurality of memory access requests to be issued to a memory device, the memory access requests including a store request and a load request, and a controller which changes an order of the store and load requests so that the order includes a string of the store requests and a string of the load requests.

Abstract: A cache memory system that is connected to a computation device and a memory device includes: a data array that includes a plurality of blocks composed of a plurality of words; a storage unit that, with respect to a block, which stores data in at least one of said words, from among the plurality of blocks, stores an address group of the memory device that is placed in correspondence with that block; a write unit that, when an address from the computation device is not in the storage unit on receiving a write instruction from the computation device, allocates any of the plurality of blocks as a block for writing, and writes the data from the computation device to any word in the block for writing; a word state storage unit that stores word information indicating one or more words, to which the data have been written by the write unit, from among words in the block for writing; and a read unit that, upon having read the data from words indicated by the word information when receiving a read instruction from the

Abstract: A cache memory system, which is individually connected to each of a plurality of arithmetic units that access a shared memory to carry out parallel processing, includes: a data array that has a plurality of blocks that are composed of a plurality of words; a storage unit that, with respect to a block, which stores data in at least one of the words, among the plurality of blocks, stores an address group of the shared memory that is placed in correspondence with that block; a write unit that, when an address from said arithmetic unit is not in the storage unit at the time of writing of data from the arithmetic unit, allocates any of the plurality of blocks as a block for writing, places any word in that block for writing in correspondence with the address, and writes the data from the arithmetic unit to the word; a word state storage unit that stores word state information for specifying a word, into which the data from the arithmetic unit have been written, in association with an address that has been placed i

Abstract: A transmitter 43 transmits a write address (i.e., address translation packet before sending the first data packet of a command). A receiver 5, when receiving the address translation packet, executes address translation of a write address. The receiver 5 also preliminarily executes address translation in advance during inter-processor communication for reducing overhead of address translation in the destination processor that occurs for each page. The transmitter reports the total number of pages in advance for suppressing wasteful address translation subsequent to the last page.

Abstract: The present invention is directed to providing an interprocessor communication system capable of obviating degradation of the performance in an interprocessor communication caused by the processing to avoid a page fault. In this system, a source processor transmits a check packet directly after successive data is transmitted by the interprocessor communication, to confirm whether or not a page fault takes place on the receiver side. The source processor carries out no processing in the case that no page fault takes place, and, in the case that a page fault takes place, the data in the page-faulty page is retransmitted. The destination processor stores the logical page numbers of the page-faulty pages in the main memory to utilize the data retransmission. Furthermore, the destination processor confirms whether or not the page faults occur in the identical page and if that is the case, no interrupt is raised so as to avoid too frequent interrupts.

Abstract: A transmitter 43 transmits a write address (i.e., address translation packet before sending the first data packet of a command). A receiver 5, when receiving the address translation packet, executes address translation of a write address. The receiver 5 also preliminarily executes address translation in advance during inter-processor communication for reducing overhead of address translation in the destination processor that occurs for each page. The transmitter reports the total number of pages in advance for suppressing wasteful address translation subsequent to the last page.

Abstract: A packet switch provides a write signal when processing of a packet in a FIFO memory is started, and outputs the write signal to the preceding stage. Meanwhile, the writing side manages whether a FIFO memory in the next stage is in a write-enabled state, and renders it into a write-disabled state in response to writing of a packet. The writing side also renders the FIFO memory of the next stage into a write-enabled state in response to a write-enable signal from the next stage.

Abstract: A packet is held in a FIFO memory through a network. The packet includes a header and data. The header includes fields of a packet type, a data length, and a designation for a processor. The packet type field defines whether its packet is either a single-cast packet or a multi-cast packet and a designation method for a destination address. There are several methods for the destination address: first, a method using a message buffer in a memory, secondly, a method using a value of an address register previously set, and thirdly, a method designating as a destination address. The (original) entity of the address register may be reserved in the memory. In this case, different message buffers for every task identifier may also be reserved in the memory.