Patents by Inventor Yasushi Kashiwabara

Yasushi Kashiwabara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8102036
    Abstract: A semiconductor device having a GaAsFET and input and output matching circuits connected to the FET is provided. In the semiconductor device, a line, including a wire connection portion connected to the input or output matching circuit and a lead connection portion connected to an input or output lead which is connected to an external circuit, is formed in such a manner that a line width at the wire connection portion is wider than that at the lead connection portion. With the semiconductor device, the number of wires connecting the input or output matching circuits with the wire connection portion can be increased.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: January 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasushi Kashiwabara
  • Publication number: 20100237486
    Abstract: A semiconductor device including: a base substrate; a frame body mounted on the base substrate and formed with a recessed portion in each of both side faces thereof opposing to each other; a semiconductor chip mounted on the base substrate within an area of the frame body; a dielectric block inserted into the recessed portion in the frame body; a waveguide formed on a surface of the dielectric block and electrically connected with the semiconductor chip; a plurality of protection patterns respectively formed along the waveguide at positions spaced from the waveguide on both sides of the waveguide on the surface of the dielectric block; and a metal layer formed on at least each of the both side faces of the dielectric block opposing to each other by plating.
    Type: Application
    Filed: February 23, 2010
    Publication date: September 23, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yasushi KASHIWABARA
  • Publication number: 20100109165
    Abstract: A semiconductor device having a GaAsFET and input and output matching circuits connected to the FET is provided. In the semiconductor device, a line, including a wire connection portion connected to the input or output matching circuit and a lead connection portion connected to an input or output lead which is connected to an external circuit, is formed in such a manner that a line width at the wire connection portion is wider than that at the lead connection portion. With the semiconductor device, the number of wires connecting the input or output matching circuits with the wire connection portion can be increased.
    Type: Application
    Filed: July 29, 2009
    Publication date: May 6, 2010
    Applicant: Kabushiki Kasiha Toshiba
    Inventor: Yasushi KASHIWABARA