Patents by Inventor Yasushi Kawase
Yasushi Kawase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230289222Abstract: A control system includes a task assigning unit, a task processing execution unit, and a reassigning unit. The task assigning unit divides a plurality of tasks dispersed in space into a plurality of groups each including one or more tasks and assign the plurality of respective groups to a plurality of respective objects of which states are changeable in the space. The task processing execution unit executes control for causing the respective objects to process the tasks of the assigned group. The reassigning unit assigns, when a processing status of a task satisfies a condition decided in advance, a task of which processing has not been ended in another group to the object that has completed processing of all the tasks of the assigned group.Type: ApplicationFiled: March 9, 2023Publication date: September 14, 2023Applicants: KYOTO UNIVERSITY, TOKYO INSTITUTE OF TECHNOLOGY, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kazuhisa MAKINO, Akitoshi Kawamura, Yasushi Kawase, Hanna Kawase Sumita, Hiromichi Goko
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Patent number: 8345480Abstract: The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.Type: GrantFiled: November 28, 2011Date of Patent: January 1, 2013Assignee: Renesas Electronics CorporationInventors: Yasushi Kawase, Susumu Ishida, Takesada Akiba, Yasushi Nagata, Naoki Miyamoto, Kazuyoshi Shiba
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Publication number: 20120069670Abstract: The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.Type: ApplicationFiled: November 28, 2011Publication date: March 22, 2012Inventors: Yasushi Kawase, Susumu Ishida, Takesada Akiba, Yasushi Nagata, Naoki Miyamoto, Kazuyoshi Shiba
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Patent number: 8089810Abstract: The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.Type: GrantFiled: September 25, 2010Date of Patent: January 3, 2012Assignee: Renesas Electronics CorporationInventors: Yasushi Kawase, Susumu Ishida, Takesada Akiba, Yasushi Nagata, Naoki Miyamoto, Kazuyoshi Shiba
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Publication number: 20110012906Abstract: The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.Type: ApplicationFiled: September 25, 2010Publication date: January 20, 2011Inventors: Yasushi KAWASE, Susumu Ishida, Takesada Akiba, Yasushi Nagata, Naoki Miyamoto, Kazuyoshi Shiba
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Patent number: 7826264Abstract: The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.Type: GrantFiled: May 26, 2006Date of Patent: November 2, 2010Assignee: Renesas Electronics CorporationInventors: Yasushi Kawase, Susumu Ishida, Takesada Akiba, Yasushi Nagata, Naoki Miyamoto, Kazuyoshi Shiba
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Patent number: 7342562Abstract: By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained. A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp (VCI?VCOML)/?t, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp (VCOMH?VCI)/?t. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2.Type: GrantFiled: April 23, 2004Date of Patent: March 11, 2008Assignee: Renesas Technology Corp.Inventors: Yasushi Kawase, Takesada Akiba, Kazuya Endo, Goro Sakamaki
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Publication number: 20070296665Abstract: By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained. A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp (VCI?VCOML)/?t, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp (VCOMH?VCI)/?t. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2.Type: ApplicationFiled: August 24, 2007Publication date: December 27, 2007Inventors: Yasushi Kawase, Takesada Akiba, Kazuya Endo, Goro Sakamaki
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Patent number: 7203116Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.Type: GrantFiled: June 7, 2006Date of Patent: April 10, 2007Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.Inventors: Hideharu Yahata, Masashi Horiguchi, Yoshikazu Saitoh, Yasushi Kawase
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Patent number: 7199648Abstract: A semiconductor integrated circuit is provided having first and second logic circuits coupled to first and second sub-power supply lines, respectively. First and second switching transistors are also provided to connect the first and second sub-power supply lines to a main power supply line. The first and second switching transistors are kept off in an operation stop state of the first and second logic circuits, and are kept on in operable state of the first and second logic circuits.Type: GrantFiled: June 3, 2004Date of Patent: April 3, 2007Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Masashi Horiguchi, Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, Kazuhiko Kajigaya
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Publication number: 20060267903Abstract: The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.Type: ApplicationFiled: May 26, 2006Publication date: November 30, 2006Inventors: Yasushi Kawase, Susumu Ishida, Takesada Akiba, Yasushi Nagata, Naoki Miyamoto, Kazuyoshi Shiba
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Publication number: 20060227642Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.Type: ApplicationFiled: June 7, 2006Publication date: October 12, 2006Inventors: Hideharu Yahata, Masashi Horiguchi, Yoshikazu Saitoh, Yasushi Kawase
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Patent number: 7082063Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.Type: GrantFiled: June 29, 2005Date of Patent: July 25, 2006Assignees: Renesas Technology Corporation, Hitachi Device Engineering Co., Ltd.Inventors: Hideharu Yahata, Masashi Horiguchi, Yoshikazu Saitoh, Yasushi Kawase
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Publication number: 20050237839Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.Type: ApplicationFiled: June 29, 2005Publication date: October 27, 2005Inventors: Hideharu Yahata, Masashi Horiguchi, Yoshikazu Saitoh, Yasushi Kawase
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Patent number: 6928017Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory in formation from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.Type: GrantFiled: August 8, 2003Date of Patent: August 9, 2005Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.Inventors: Hideharu Yahata, Masashi Horiguchi, Yoshikazu Saitoh, Yasushi Kawase
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Publication number: 20050073895Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.Type: ApplicationFiled: August 8, 2003Publication date: April 7, 2005Inventors: Hideharu Yahata, Masashi Horiguchi, Yoshikazu Saitoh, Yasushi Kawase
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Patent number: RE38944Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.Type: GrantFiled: October 12, 2001Date of Patent: January 24, 2006Assignees: Hitachi, Ltd., Hitach Device Engineering Co., Ltd.Inventors: Tsugio Takahashi, Goro Kitsukawa, Takesada Akiba, Yasushi Kawase, Masayuki Nakamura
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Patent number: RE40356Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.Type: GrantFiled: July 8, 2005Date of Patent: June 3, 2008Assignee: Hitachi, Ltd.Inventors: Tsugio Takahashi, Goro Kitsukawa, Takesada Akiba, Yasushi Kawase, Masayuki Nakamura
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Patent number: RE41379Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.Type: GrantFiled: June 7, 2007Date of Patent: June 15, 2010Assignee: Rising Silicon, Inc.Inventors: Tsugio Takahashi, Goro Kitsukawa, Takesada Akiba, Yasushi Kawase, Masayuki Nakamura
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Patent number: RE42659Abstract: A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion.Type: GrantFiled: June 7, 2007Date of Patent: August 30, 2011Inventors: Tsugio Takahashi, Goro Kitsukawa, Takesada Akiba, Yasushi Kawase, Masayuki Nakamura