Abstract: A base station allocation support apparatus includes a first calculation unit that calculates radio wave propagation attenuation values between a plurality of wireless terminals in a certain area based on position information of each of the plurality of wireless terminals and information indicating a layout of the area, a clustering unit that performs clustering on the plurality of wireless terminals based on the radio wave propagation attenuation values; and a determination unit that determines an arrangement position of a wireless base station with respect to the wireless terminals based on a result of the clustering.

Abstract: When binary pixel data is written to a pixel circuit, of an H-level (3V) and a L-level (0V), a voltage of the level indicating the binary pixel data is held at a first node, and a voltage of the inverted level thereof is held at a second node. The first and second nodes are connected to a third node via N-channel transistors, respectively, and first and second selection control signals are supplied to gate terminals of the transistors, respectively. Voltage levels of the first and second selection control signals are periodically switched between 5V indicating the H-level and 0V indicating the L-level in a mutually inverted manner. As a result, the voltage of the first node and the voltage of the second node are alternately selected and applied to a pixel electrode of a display element.

Abstract: When binary pixel data is written to a pixel circuit, of an H-level (3V) and a L-level (0V), a voltage of the level indicating the binary pixel data is held at a first node, and a voltage of the inverted level thereof is held at a second node. The first and second nodes are connected to a third node via N-channel transistors, respectively, and first and second selection control signals are supplied to gate terminals of the transistors, respectively. Voltage levels of the first and second selection control signals are periodically switched between 5V indicating the H-level and 0V indicating the L-level in a mutually inverted manner. As a result, the voltage of the first node and the voltage of the second node are alternately selected and applied to a pixel electrode of a display element.

Abstract: A signal obtained through sampling a gate start pulse signal GSP by using one of a plurality of gate clock signals is supplied as a shift pulse for a forward shift action (a forward shift start pulse signal) to the first stage of a plurality of stages constituting a bidirectional shift register, and a signal obtained through sampling the gate start pulse signal GSP by using another one of the plurality of gate clock signals is supplied as a shift pulse for a backward shift action (a backward shift start pulse signal) to the last stage of the plurality of stages constituting the bidirectional shift register.

Abstract: A method for producing phosphorus in which a reaction for forming gaseous phosphorus (g) by bringing phosphorus oxide generated by heating a liquid phosphoric acid compound into contact with a carbon material to reduce the phosphorus oxide and for condensing the gaseous phosphorus (g) to obtain liquid phosphorus (L) is conducted by a flow reaction with a nonoxidizing gas flow, wherein the reduction reaction of the phosphorus oxide is conducted in a carbon material-packed bed, and the condensation of the formed gaseous phosphorus (g) is substantially conducted in a condensation accelerator-packed bed which is disposed downstream of the carbon material-packed bed in contact with the carbon material-packed bed.

Abstract: A signal obtained through sampling a gate start pulse signal GSP by using one of a plurality of gate clock signals is supplied as a shift pulse for a forward shift action (a forward shift start pulse signal) to the first stage of a plurality of stages constituting a bidirectional shift register, and a signal obtained through sampling the gate start pulse signal GSP by using another one of the plurality of gate clock signals is supplied as a shift pulse for a backward shift action (a backward shift start pulse signal) to the last stage of the plurality of stages constituting the bidirectional shift register.

Abstract: A display device includes a pixel unit, a binary driver, and a timing generator. The display device is an active matrix display device configured to receive a data signal including image data and other data different from the image data. The pixel unit includes a memory configured to store the image data. The binary driver includes a first holding circuit configured to hold the image data and at least one second holding circuit configured to hold the other data. The timing generator is configured to generate a drive signal used for driving the binary driver.

Abstract: A display device includes a pixel unit, a binary driver, and a timing generator. The display device is an active matrix display device configured to receive a data signal including image data and other data different from the image data. The pixel unit includes a memory configured to store the image data. The binary driver includes a first holding circuit configured to hold the image data and at least one second holding circuit configured to hold the other data. The timing generator is configured to generate a drive signal used for driving the binary driver.

Abstract: A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.

Abstract: A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.

Abstract: Provided is a shift register circuit capable of preventing occurrence of malfunction caused by a threshold shift of a thin-film transistor due to an influence of external light. A unit circuit constituting each stage of the shift register circuit includes a plurality of thin-film transistors. The plurality of thin-film transistors are categorized into a first group (T2, T4, T9) whose on-off state is controlled at relatively high on-duty and a second group (T1, T3, T5, T6, T7, T8) whose on-off state is controlled at relatively low on-duty. In such a configuration, a light shielding film (LS) is provided only for the thin-film transistor included in one of the first group and the second group.

Abstract: Provided is a liquid crystal display device that has excellent visibility while using a protective film comprising a polyester film. The liquid crystal display device comprises a backlight light source, and a liquid crystal cell disposed between two polarizers; the backlight light source being a white light-emitting diode; each of the polarizers comprising a polarizing film and protective films laminated on both sides of the polarizing film; and at least one of the protective films being a polyester film having a retardation of 3,000 to 30,000 nm.

Abstract: Regarding a variant-form display (typically, a display device having a shape in which a non-display region is provided between display regions), it achieves a narrower picture-frame than conventional displays. In a display device having a non-rectangular display region, sub gate drivers are provided in a region where bypass wiring lines are conventionally disposed, for example, as follows. In a display device having a right-angled U-shaped display region having two projecting portions (a left projecting portion and a right projecting portion, a sub gate driver for driving some gate bus lines disposed in the left projecting portion is provided, in a region in a recessed portion, in a vicinity of the left projecting portion, and a sub gate driver for driving some gate bus lines disposed in the right projecting portion is provided, in a region in the recessed portion, in a vicinity of the right projecting portion.

Abstract: A unit circuit 11 of a shift register is provided with a transistor Tr10 for supplying an off potential to a node n1 via a drain terminal when performing an all-on output. An all-on control signal AON is supplied to a gate terminal of the transistor Tr10. Instead of a low level potential VSS supplied from a power supply circuit, an initialization signal INIT which becomes a low level when performing the all-on output supplied to a source terminal of the transistor Tr10. Since the all-on signal AON and the initialization signal INIT are supplied from an outside, even if noise is imposed on the low level potential VSS when performing the normal operation, the transistor Tr10 does not turn on and charge does not escape from the node 1. With this, it is possible to prevent malfunction of the shift register due to noise imposed on the off potential supplied from the power supply circuit.

Abstract: A power control apparatus used in a power control system provided with a fuel cell which generates power while a current sensor is detecting forward power flow, a solar cell, and a storage battery comprises a pseudo-output unit configured to generate a pseudo current to be detected by the current sensor; and a controller configured to control the pseudo-output unit. The controller acquires at least one of a charge level of the storage battery and an output value of the solar cell and, based on at least one of the charge level and the output value, adjusts the pseudo current detected by the current sensor to control a power generation amount of the fuel.

Abstract: A unit circuit 11 of a shift register is provided with a transistor Tr8 having a drain terminal connected to a node N2, a source terminal to which an off potential is applied, and a gate terminal connected to an output terminal OUT, in order to stabilize a potential of the node N2. The unit circuit 11 is further provided with a transistor Tr9 having a drain terminal connected to the output terminal OUT, a source terminal to which the off potential is applied, and a gate terminal to which an initialization signal INIT is supplied. With this, when performing an initialization, it is possible to control the potential of the node N2 to be a desired level and initialize the shift register certainly, irrespective of a state of the transistor Tr8 before the initialization.

Abstract: The invention provides a liquid crystal display device, as well as a polarizer and a protective film suitable for the liquid crystal display device. The liquid crystal display device comprises a backlight light source, two polarizers, and a liquid crystal cell disposed between the two polarizers; the backlight light source being a white light-emitting diode light source; each of the two polarizers comprising a polarizing film and protective films laminated on both sides of the polarizing film; at least one of the protective films being a polyester film having an adhesion-facilitating layer; the polyester film having a retardation of 3,000 to 30,000 nm; and the adhesion-facilitating layer comprising a polyester resin (A) and a polyvinyl alcohol resin (B).

Abstract: A transistor includes gate electrodes and light blocking films. The light blocking films are provided in a layer lower than a layer in which the gate electrodes are provided, overlap the respective gate electrodes as viewed in a plan view, shield a channel portion from light, and are electrically isolated.

Abstract: The present invention reliably and sufficiently corrects a voltage variation in data signal lines in a display device resulting when sampling analog video signals, while suppressing increase in layout area. In a data signal line drive circuit of an active matrix liquid crystal display device, a video signal Svi is sampled by an Nch transistor (SWk) which has a parasitic capacitance (Cgd) that causes a voltage drop in a data signal line SL3(i?1)+k (i=1 through n; k=1, 2, 3). To correct this, an inversion delayer (342) makes logical inversion of the transistor (SWk)'s control signal Sck and delays the inverted signal for a predetermined time to generate an inversion delayed signal Srdk, and applies this inversion delayed signal Srd to the data signal line 3(i?1)+k via a correction capacitance element (Cc). The inversion delayer (342) makes the inversion delayed signal Srdk start its change from an L level voltage to a H level voltage after the Nch transistor (SWk) has assumed an OFF state.

Abstract: The invention provides a liquid crystal display device, as well as a polarizer and a protective film suitable for the liquid crystal display device. The liquid crystal display device comprises a backlight light source, two polarizers, and a liquid crystal cell disposed between the two polarizers; the backlight light source being a white light-emitting diode light source; each of the two polarizers comprising a polarizing film and protective films laminated on both sides of the polarizing film; at least one of the protective films being a polyester film having an adhesion-facilitating layer; the polyester film having a retardation of 3,000 to 30,000 nm; and the adhesion-facilitating layer comprising a polyester resin (A) and a polyvinyl alcohol resin (B).