Patents by Inventor Yasushi Tamura

Yasushi Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240039184
    Abstract: A terminal block that includes: a first terminal electrically connected to an electrical component; and a second terminal electrically connected to the first terminal, wherein a current sensor for detecting a current that flows through the first terminal or the second terminal is integrated with the first terminal or the second terminal.
    Type: Application
    Filed: November 30, 2021
    Publication date: February 1, 2024
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Tomoki ABE, Takuya HANYU, Daisuke HASHIMOTO, Masaharu SUETANI, Kentaro TACHI, Dohyung KIM, Yasushi TAMURA
  • Patent number: 11858045
    Abstract: Provided is a Fe-based sintered body which has both of a high hardness and a high thermal conductivity and which can be more stably produced. The Fe-based sintered body includes: a matrix (1) containing Fe as a main component; and a hard phase (4) dispersed in the matrix (1). The matrix (1) is formed in a network shape and contains ?Fe. The hard phase (4) contains TiC.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: January 2, 2024
    Assignees: Hiroshima University, Y-tec Corporation, keylex corporation, Mazda Motor Corporation
    Inventors: Kazuhiro Matsugi, Yujiao Ke, Zhefeng Xu, Kenjiro Sugio, Yongbum Choi, Gen Sasaki, Hajime Suetsugu, Hiroki Kondo, Hideki Manabe, Kyotaro Yamane, Kenichi Hatakeyama, Keizo Kawasaki, Tsuyoshi Itaoka, Shinsaku Seno, Yasushi Tamura, Ichirou Ino, Yoshihide Hirao
  • Patent number: 11823938
    Abstract: A mounting device comprises a recognition mechanism and a control unit. The recognition mechanism recognizes a chip recognition mark and a substrate recognition mark through a mounting head and from above the mounting head and is movable in an in-plane direction of a substrate surface of a substrate. The control unit is connected to the recognition mechanism, calculates an amount of misalignment between a chip component and the substrate from position information about the chip recognition mark and the substrate recognition mark obtained from the recognition mechanism, and performs positioning by driving the mounting head and/or the substrate stage according to the amount of misalignment. The recognition mechanism has a chip recognition sensor for recognizing the chip recognition mark and a substrate recognition sensor for recognizing the substrate recognition mark provided independently so that focal positions thereof are different via a common optical axis path.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: November 21, 2023
    Assignee: TORAY ENGINEERING CO., LTD.
    Inventor: Yasushi Tamura
  • Publication number: 20220231537
    Abstract: A conversion device is a conversion device that converts power supplied from a power supply device including a plurality of battery units, and includes a plurality of power conversion units. Each of the plurality of power conversion units is connected to the plurality of battery units such that a voltage within a range of a breakdown voltage of the power conversion unit is input.
    Type: Application
    Filed: May 10, 2019
    Publication date: July 21, 2022
    Inventors: Masayoshi Hirota, Takafumi Kawakami, Yasushi Tamura
  • Publication number: 20210351057
    Abstract: a mounting device and a mounting method is provided with which, after lowering a mounting head holding a chip component in a direction perpendicular to a substrate to bring the chip component into close contact with the substrate subsequent to positioning the chip component and the substrate, a control unit causes a recognition mechanism to start a parallel recognition operation of a chip recognition mark and a substrate recognition mark and recognize the chip recognition mark and the substrate recognition mark through the mounting head in a mounted state in which the chip component is in close contact with the substrate, and calculates mounting position accuracy of the chip component and the substrate.
    Type: Application
    Filed: July 21, 2021
    Publication date: November 11, 2021
    Inventor: Yasushi TAMURA
  • Publication number: 20210351056
    Abstract: A mounting device comprises a recognition mechanism and a control unit. The recognition mechanism recognizes a chip recognition mark and a substrate recognition mark through a mounting head and from above the mounting head and is movable in an in-plane direction of a substrate surface of a substrate. The control unit is connected to the recognition mechanism, calculates an amount of misalignment between a chip component and the substrate from position information about the chip recognition mark and the substrate recognition mark obtained from the recognition mechanism, and performs positioning by driving the mounting head and/or the substrate stage according to the amount of misalignment. The recognition mechanism has a chip recognition sensor for recognizing the chip recognition mark and a substrate recognition sensor for recognizing the substrate recognition mark provided independently so that focal positions thereof are different via a common optical axis path.
    Type: Application
    Filed: July 21, 2021
    Publication date: November 11, 2021
    Inventor: Yasushi TAMURA
  • Publication number: 20210316361
    Abstract: Provided is a method of producing a composite having high strength and high thermal conductivity. The method includes: an alloy preparation step including preparing an alloy which is a solid solution containing ?-Fe as a solvent and at least one type of ?-phase stabilizing element as a solute; a first mixing step including mixing at least one type of ?-phase stabilizing element in powder form and SiC to prepare a first mixture; a second mixing step including mixing the alloy and the first mixture to prepare a second mixture; and a sintering step including sintering the second mixture.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 14, 2021
    Inventors: Kenjiro SUGIO, Takuya TAKAHASHI, Hitoshi SAWADA, Gen SASAKI, Kazuhiro MATSUGI, Yongbum CHOI, Zhefeng XU, Hajime SUETSUGU, Hiroki KONDO, Hideki MANABE, Kyotaro YAMANE, Kenichi HATAKEYAMA, Keizo KAWASAKI, Tsuyoshi ITAOKA, Shinsaku SENO, Yasushi TAMURA, Ichirou INO, Yoshihide HIRAO
  • Publication number: 20210308756
    Abstract: Provided is a Fe-based sintered body which has both of a high hardness and a high thermal conductivity and which can be more stably produced. The Fe-based sintered body includes: a matrix (1) containing Fe as a main component; and a hard phase (4) dispersed in the matrix (1). The matrix (1) is formed in a network shape and contains ?Fe. The hard phase (4) contains TiC.
    Type: Application
    Filed: July 24, 2019
    Publication date: October 7, 2021
    Inventors: Kazuhiro MATSUGI, Yujiao KE, Zhefeng XU, Kenjiro SUGIO, Yongbum CHOI, Gen SASAKI, Hajime SUETSUGU, Hiroki KONDO, Hideki MANABE, Kyotaro YAMANE, Kenichi HATAKEYAMA, Keizo KAWASAKI, Tsuyoshi ITAOKA, Shinsaku SENO, Yasushi TAMURA, Ichirou INO, Yoshihide HIRAO
  • Patent number: 10991477
    Abstract: An insulated electrical cable includes: a conductor; and an insulating layer that is laminated on an outer peripheral surface of the conductor and includes a polyimide as a main component, wherein the insulating layer includes a plurality of pores, and wherein a porosity of the insulating layer is greater than or equal to 25% by volume and less than or equal to 60% by volume.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: April 27, 2021
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC WINTEC, INC.
    Inventors: Shinya Ota, Masaaki Yamauchi, Hideaki Saito, Shuhei Maeda, Yasushi Tamura, Kengo Yoshida
  • Patent number: 10962498
    Abstract: A method for producing an insulated electric wire includes a step of preparing a conductor having a linear shape; a step of forming an insulating coating so as to cover a surface on an outer peripheral side of the conductor to obtain an insulated electric wire that includes the conductor and the insulating coating covering the conductor; and a step of measuring a first electrostatic capacity between the insulated electric wire and a first electrode disposed outside in a radial direction of the insulated electric wire so as to face an outer peripheral surface of the insulated electric wire while transporting the insulated electric wire in a longitudinal direction of the conductor, and inspecting a formation state of the insulating coating, the formation state including a formation state of a defective portion in the insulating coating, on the basis of a change in the first electrostatic capacity.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 30, 2021
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC WINTEC, INC.
    Inventors: Shinya Ota, Masaaki Yamauchi, Jun Sugawara, Yasushi Tamura, Kengo Yoshida, Takao Inoue, Hiroji Sugimoto
  • Patent number: 10832829
    Abstract: An insulated electric wire includes a linear conductor and one or a plurality of insulating layers formed on an outer peripheral surface of the conductor. At least one of the one or plurality of insulating layers contains a plurality of pores, outer shells are disposed on peripheries of the pores, and the outer shells are derived from shells of hollow-forming particles having a core-shell structure. A varnish for forming an insulating layer contains a resin composition forming a matrix and hollow-forming particles having a core-shell structure and dispersed in the resin composition. In the varnish, cores of the hollow-forming particles contain a thermally decomposable resin as a main component, and shells of the hollow-forming particles contain a main component having a higher thermal decomposition temperature than the thermally decomposable resin.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: November 10, 2020
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC WINTEC, INC.
    Inventors: Shinya Ota, Shuhei Maeda, Hideaki Saito, Jun Sugawara, Masaaki Yamauchi, Yasushi Tamura, Kengo Yoshida, Yudai Furuya, Yuji Hatanaka
  • Patent number: 10770750
    Abstract: A lithium ion conductor includes a first lithium ion conductor that contains at least one selected from among oxide crystals and glass ceramics, and a second lithium ion conductor that has a sintering temperature of not more than 600° C. The lithium ion conductivity of the first lithium ion conductor is higher than the lithium ion conductivity of the second lithium ion conductor.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: September 8, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Keisuke Shimizu, Masamitsu Suzuki, Tatsuya Furuya, Kenji Kishimoto, Go Sudo, Yasushi Tamura, Yumiko Yoshida
  • Publication number: 20200152348
    Abstract: An insulated electrical cable according to one aspect of the present invention is an insulated electrical cable including: a conductor; and an insulating layer that is laminated on an outer peripheral surface of the conductor and includes a polyimide as a main component, wherein the insulating layer includes a plurality of pores, and wherein a porosity of the insulating layer is greater than or equal to 25% by volume and less than or equal to 60% by volume.
    Type: Application
    Filed: April 26, 2018
    Publication date: May 14, 2020
    Inventors: Shinya OTA, Masaaki YAMAUCHI, Hideaki SAITO, Shuhei MAEDA, Yasushi TAMURA, Kengo YOSHIDA
  • Publication number: 20200135360
    Abstract: An insulated electric wire includes a linear conductor and an insulating film disposed to surround the periphery of the conductor. The insulating film includes a polyimide layer formed of a polyimide that has a molecular structure including a PMDA-ODA-type repeating unit A and a BPDA-ODA-type repeating unit B, the mole fraction [B×100/(A+B)] (% by mole) represented by the percentage of the number of moles of the repeating unit B to the total number of moles of the repeating unit A and the repeating unit B being 25% or more by mole and 95% or less by mole. The polyimide layer has a plurality of pores. The pores occupy 5% or more by volume and 80% or less by volume of the polyimide layer.
    Type: Application
    Filed: June 15, 2018
    Publication date: April 30, 2020
    Inventors: Shuhei MAEDA, Masaaki YAMAUCHI, Shinya OTA, Hideaki SAITO, Yasushi TAMURA, Kengo YOSHIDA, Shigenori HOMMA
  • Publication number: 20200118705
    Abstract: An insulated electric wire includes a conductor that has a linear shape and an insulating film that is formed to cover the periphery of the conductor. The insulating film is formed of a polyimide that has a molecular structure including a PMDA-ODA-type repeating unit A and a BPDA-ODA-type repeating unit B, the mole ratio [B/(A+B)]×100 (% by mole) of the number of moles of the repeating unit B to the total number of moles of the repeating unit A and the repeating unit B being more than 55% by mole. A first sample of the insulating film with a separation elongation of 7% has a ratio M60/M10 of 1.2 or more, or a second sample of the insulating film with a separation elongation of 40% has a ratio M30/M10 of 1.2 or more.
    Type: Application
    Filed: June 15, 2018
    Publication date: April 16, 2020
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC WINTEC, INC.
    Inventors: Shuhei MAEDA, Masaaki YAMAUCHI, Tokiko UMEMOTO, Yasushi TAMURA
  • Patent number: 10607750
    Abstract: An insulated wire according to one embodiment of the present invention includes a linear conductor, and one or a plurality of insulating layers that are laminated on an outer peripheral surface of the conductor, wherein at least one layer of the one or plurality of insulating layers includes a plurality of pores, and a closed porosity within the plurality of pores is 80% by volume or higher.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: March 31, 2020
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC WINTEC, INC.
    Inventors: Shinya Ota, Masaaki Yamauchi, Kengo Yoshida, Yasushi Tamura
  • Publication number: 20200033286
    Abstract: A method for producing an insulated electric wire includes a step of preparing a conductor having a linear shape; a step of forming an insulating coating so as to cover a surface on an outer peripheral side of the conductor to obtain an insulated electric wire that includes the conductor and the insulating coating covering the conductor; and a step of measuring a first electrostatic capacity between the insulated electric wire and a first electrode disposed outside in a radial direction of the insulated electric wire so as to face an outer peripheral surface of the insulated electric wire while transporting the insulated electric wire in a longitudinal direction of the conductor, and inspecting a formation state of the insulating coating, the formation state including a formation state of a defective portion in the insulating coating, on the basis of a change in the first electrostatic capacity.
    Type: Application
    Filed: October 20, 2017
    Publication date: January 30, 2020
    Inventors: Shinya OTA, Masaaki YAMAUCHI, Jun SUGAWARA, Yasushi TAMURA, Kengo YOSHIDA, Takao INOUE, Hiroji SUGIMOTO
  • Publication number: 20190371496
    Abstract: An insulated wire according to one embodiment of the present invention includes a linear conductor, and one or a plurality of insulating layers that are laminated on an outer peripheral surface of the conductor, wherein at least one layer of the one or plurality of insulating layers includes a plurality of pores, and a closed porosity within the plurality of pores is 80% by volume or higher.
    Type: Application
    Filed: March 21, 2018
    Publication date: December 5, 2019
    Inventors: Shinya OTA, Masaaki YAMAUCHI, Kengo YOSHIDA, Yasushi TAMURA
  • Patent number: 10468153
    Abstract: An insulated electric wire includes a linear conductor and one or more of insulating layers formed on an outer peripheral surface of the conductor. In the insulated electric wire, at least one of the one or more of insulating layers has a plurality of pores, outer shells are disposed on peripheries of the pores, and each of the outer shells has a plurality of projections on an outer surface thereof.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: November 5, 2019
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC WINTEC, INC.
    Inventors: Shinya Ota, Masaaki Yamauchi, Jun Sugawara, Yasushi Tamura, Kengo Yoshida
  • Publication number: 20190074106
    Abstract: An insulated electric wire includes a linear conductor and one or more of insulating layers formed on an outer peripheral surface of the conductor. In the insulated electric wire, at least one of the one or more of insulating layers has a plurality of pores, outer shells are disposed on peripheries of the pores, and each of the outer shells has a plurality of projections on an outer surface thereof.
    Type: Application
    Filed: May 12, 2017
    Publication date: March 7, 2019
    Inventors: Shinya OTA, Masaaki YAMAUCHI, Jun SUGAWARA, Yasushi TAMURA, Kengo YOSHIDA