Abstract: In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

Abstract: In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

Abstract: In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

Abstract: A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0 V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.

Abstract: A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

Abstract: There is a case where a memory cell brought to an over-erase (depletion) state if the erasing time is too long, for example, in an electrically erasable non-volatile semiconductor memory device. In this case, the transistor constituting the memory cell is always in ON state and causes erroneous operation. Therefore, it is detected whether there is any memory cell in the over-erase state or not after erasing in each memory cell, and if any memory cell is detected being in the over-erase state, tunnel writing is performed in each memory cell. Specifically, electrons are injected into the floating gate of the transistor constituting each memory cell by a tunnel phenomenon. This causes the memory cell in the over-erase state to recover to a normal state. Detection of the over-erase state and recovery from it are performed by an over-erase correcting circuit 72.

Abstract: A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

Abstract: A non-volatile semiconductor memory device according to the present invention comprises a plurality of memory cells including floating gates, an injecting device for injecting electrons to the floating gate of each of the memory cells, a removing device for removing electrons from the floating gate of each of the memory cells, an erasure instructing device for instructing erasing operation, and a controlling device responsive to an instruction output from the erasure instructing device for controlling the injecting device such that electrons are simultaneously injected to all the floating gates of the memory cells which are to be erased before the removing operation by the removing device.

Abstract: A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.

Abstract: A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0 V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.

Abstract: In a programming mode of operation of a flash type non-volatile semiconductor memory device, an erase voltage pulse is applied a memory cell to bring the memory cell into an erased state. Then, an after-erase writing operation is executed for a memory cell having a threshold voltage lower than a predetermined threshold voltage under the condition of small change in threshold voltage. Alternatively, an erase voltage pulse is applied only to a memory cell having a threshold voltage greater than a predetermined threshold voltage to carry out erasing. Also, after a memory cell is brought to a depletion state by application of an erase voltage pulse, data writing of "0" and "1" is carried out by injection of electrons into the floating gate. The electron injection rate to the floating gate for writing data "0" is set to be greater than that for writing data "1". The state of storing data "1" corresponds to an erase state.

Abstract: A nonvolatile semiconductor memory device has a plurality of memory cells, which are arranged in a matrix form having rows and columns and each have floating a gate for holding an information charge, a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a high voltage generator for generating a negative high voltage. The high voltage generator is connected to each word line and has a capacitor to which a predetermined clock is applied in response to a signal for selecting word lines. The semiconductor memory device further comprises an erasing device, which applies the negative high voltage generated by, the high voltage generator to the word line selected by the selection signal in the erasing operation. The erasing device grounds the source line connected to the source of the corresponding memory cell.

Abstract: The semiconductor device includes a voltage generator for generating selectively a signal of a first level or a second level onto a first supply line, and a voltage converter using voltage signals on the first supply line and a second supply line for producing a signal of the voltage level on the first or the second supply line in accordance with an input signal, and a voltage level shifter for detecting the level of the voltage on the first supply line to shift in voltage level a signal on the second power supply line toward the first level when the voltage on the first supply line approaches the first level. The difference of the voltages on the first and second supply lines can be reduced to improve the break-down characteristics of a transistor included in the voltage converter, resulting in a reliable semiconductor device.

Abstract: A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0 V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.

Abstract: Disclosed is a flash EEPROM including a voltage lowering circuit therein for lowering an externally applied high voltage serving as a source of an erase pulse to a predetermined voltage in a range in which a tunnel phenomenon sufficiently occurs in memory cells. The voltage lowered by the voltage lowering circuit is converted into a pulse of a small width, and the converted pulse is then applied as an erase pulse to the memory cells. A flash EEPROM including a memory cell array divided into first and second blocks is also disclosed. An erase pulse applying circuit for applying the voltage lowered by the voltage lowering circuit as an erase pulse to the memory cells, and an erase verify circuit for erase verifying are provided for each of the first and second blocks. The erase pulse applying circuit and the erase verify circuit corresponding to the first block and the ones corresponding to the second block are configured to operate independently.

Abstract: A flash EEPROM including a memory cell array divided into first and second blocks. Erase pulse applying circuits for applying erase pulses to memory cells and erase verifying circuits for erase-verifying the memory cells are provided one for each of those two blocks. The erase pulse applying circuit and the erase verifying circuit provided corresponding to the first block operate separately from the erase pulse applying circuit and the erase verifying circuit provided corresponding to the second block. The erase pulse applying circuits are each controlled by their corresponding erase verifying circuits. That is, each erase verifying circuit enables its corresponding erase pulse applying circuit only when detecting a memory cell in which a data erase is incomplete in the corresponding block.

Abstract: A plurality of memory cell transistors having floating gates are disposed in a matrix in the direction of row and column to form a memory cell array. The memory cell array is divided into a plurality of sectors for every predetermined row. In each sector, sector selecting transistors and sub bit lines are provided, so that erasing and programming can be made for each sector. Therefore, total erasing for sector becomes possible, and since no voltage is applied to sub bit lines and word lines of non-selected sectors, the number of operations of preventing writing into non-selected memory cells is as many as the word lines included in one sector.

Abstract: A memory cell array is electrically separated into an upper memory cell array 1a and a lower memory cell array 1b by a connection transistor group 2, when an external address signal changes. Therefore, each bit line pair in the memory cell array is separated into corresponding two bit line pairs. The potential of the bit line belonging to the selected memory cell is set to the read potential. Meanwhile, the potential of the bit line forming the pair of the bit line separated from the bit line is set to an intermediate potential between "0" read potential and "1" read potential. Then, the upper memory cell array 1a and the lower memory cell array 1b are electrically connected, whereby the bit line pairs corresponding to each memory cell array are integrated into one bit line pair. The potential difference of the two bit lines forming the integrated bit line pair is amplified by a corresponding differential amplifying type sense amplifier.