Patents by Inventor Yasushi Yamakawa

Yasushi Yamakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10090060
    Abstract: According to one embodiment, a data communication system includes: a data transmitting device that transmits a test pattern; and a data receiving device that receives the test pattern. The data receiving device receives the test pattern with every change in a threshold for determining whether received data is High or Low, compares the test pattern to an expected value for the respective changed thresholds, and selects the threshold based on the result of comparison between the test pattern and the expected value.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akihiro Fukushima, Shuji Matsumoto, Makoto Hara, Yasushi Yamakawa
  • Publication number: 20170248654
    Abstract: According to one embodiment, a data communication system includes: a data transmitting device that transmits a test pattern; and a data receiving device that receives the test pattern. The data receiving device receives the test pattern with every change in a threshold for determining whether received data is High or Low, compares the test pattern to an expected value for the respective changed thresholds, and selects the threshold based on the result of comparison between the test pattern and the expected value.
    Type: Application
    Filed: September 2, 2016
    Publication date: August 31, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akihiro FUKUSHIMA, Shuji MATSUMOTO, Makoto HARA, Yasushi YAMAKAWA
  • Patent number: 8847646
    Abstract: In a system in which the phases of a data clock signal and a data signal differ between at an input and at an output, a semiconductor integrated circuit performs a simple BER test without using external equipment and, at the same time, performs a jitter evaluation required for a margin evaluation.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: September 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasushi Yamakawa
  • Publication number: 20140240014
    Abstract: In a system in which the phases of a data clock signal and a data signal differ between at an input and at an output, a semiconductor integrated circuit performs a simple BER test without using external equipment and, at the same time, performs a jitter evaluation required for a margin evaluation.
    Type: Application
    Filed: August 9, 2013
    Publication date: August 28, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yasushi YAMAKAWA
  • Patent number: 5977934
    Abstract: An information processing apparatus for outputting a display signal to a display device includes a memory unit for storing a plurality of display specification setting instructions for specifying display specifications of a plurality of display devices having different specifications form each other, an instruction execution unit for reading one of the display specification setting instructions from the memory unit in response to an identification signal to execute the display specification setting instruction and a display controller for outputting the display signal in accordance with the display specification of the display specification setting instruction. The display signal in accordance with the display specification of the display device is inputted to the display device.
    Type: Grant
    Filed: October 7, 1996
    Date of Patent: November 2, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Wada, Yoshiaki Nomura, Yasushi Yamakawa