Patents by Inventor Yasutaka Ozaki
Yasutaka Ozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9112006Abstract: Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 ?m.Type: GrantFiled: April 21, 2014Date of Patent: August 18, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventor: Yasutaka Ozaki
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Publication number: 20140227854Abstract: Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 ?m.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Yasutaka OZAKI
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Patent number: 8742484Abstract: Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 ?m.Type: GrantFiled: January 22, 2012Date of Patent: June 3, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Yasutaka Ozaki
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Patent number: 8729619Abstract: Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 ?m.Type: GrantFiled: November 11, 2011Date of Patent: May 20, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Yasutaka Ozaki
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Publication number: 20120112316Abstract: Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 ?m.Type: ApplicationFiled: January 22, 2012Publication date: May 10, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Yasutaka OZAKI
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Publication number: 20120056300Abstract: Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 ?m.Type: ApplicationFiled: November 11, 2011Publication date: March 8, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Yasutaka OZAKI
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Patent number: 8125014Abstract: Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 ?m.Type: GrantFiled: December 5, 2005Date of Patent: February 28, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Yasutaka Ozaki
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Patent number: 7679202Abstract: A plurality of device patterns constituting part of an electronic circuit are formed over the surface of a substrate. A symbol pattern to be used for an identification sign is formed in the same layer as the device patterns. A width of the device pattern is within a pattern width range on a design rule. The symbol pattern is formed by a plurality of isolated element patterns. The element pattern is either a linear pattern or a dot pattern. A width of the element pattern is equal to or larger than 0.8 time a lower limit value of the pattern width range and equal to or smaller than 1.2 times an upper limit value of the pattern width range.Type: GrantFiled: April 24, 2007Date of Patent: March 16, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Shigeki Yoshida, Fumio Ushida, Nobuhisa Naori, Yasutaka Ozaki
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Publication number: 20090278231Abstract: The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor 44 formed over the first insulation film 26, a first hydrogen diffusion preventing film 48 formed over the first insulation film 26, covering the capacitor 44, a second insulation film 50 formed over the first hydrogen diffusion preventing film and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the first hydrogen diffusion preventing film 26 and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the second insulation film 50, second conductor plug 62 buried in a second contact hole 56 formed down to the lower electrode 38 or the upper electrode 42 of the capacitor 44, a third conductor plug 62 buried in a third contact hole 58 formed down to the first conductor plug 32, and an interconnection 64 connected toType: ApplicationFiled: July 14, 2009Publication date: November 12, 2009Applicant: Fujitsu Microelectronics LimitedInventors: Kouichi Nagai, Hideaki Kikuchi, Naoya Sashida, Yasutaka Ozaki
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Patent number: 7598557Abstract: The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor 44 formed over the first insulation film 26, a first hydrogen diffusion preventing film 48 formed over the first insulation film 26, covering the capacitor 44, a second insulation film 50 formed over the first hydrogen diffusion preventing film and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the first hydrogen diffusion preventing film 26 and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the second insulation film 50, second conductor plug 62 buried in a second contact hole 56 formed down to the lower electrode 38 or the upper electrode 42 of the capacitor 44, a third conductor plug 62 buried in a third contact hole 58 formed down to the first conductor plug 32, and an interconnection 64 connected toType: GrantFiled: January 27, 2005Date of Patent: October 6, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Kouichi Nagai, Hideaki Kikuchi, Naoya Sashida, Yasutaka Ozaki
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Patent number: 7462898Abstract: A ferroelectric capacitor is formed above a substrate and made of a lamination of a lower electrode, a capacitor ferroelectric film and an upper electrode stacked in this order. The upper electrode is made of conductive oxide and has such an oxygen concentration distribution as an oxygen concentration in a lower layer region of the upper electrode becomes lower than an oxygen concentration in an upper layer region. An interlayer insulating film covers the ferroelectric capacitor. A via hole is formed through the interlayer insulating film and reaches a position deeper than an upper surface of the upper electrode. The via hole is stopped at a position shallower than a position at which the oxygen concentration of the upper electrode becomes maximum. A conductive member contacts the upper electrode on a bottom of the via hole.Type: GrantFiled: December 8, 2005Date of Patent: December 9, 2008Assignee: Fujitsu LimitedInventor: Yasutaka Ozaki
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Publication number: 20070296091Abstract: A plurality of device patterns constituting part of an electronic circuit are formed over the surface of a substrate. A symbol pattern to be used for an identification sign is formed in the same layer as the device patterns. A width of the device pattern is within a pattern width range on a design rule. The symbol pattern is formed by a plurality of isolated element patterns. The element pattern is either a linear pattern or a dot pattern. A width of the element pattern is equal to or larger than 0.8 time a lower limit value of the pattern width range and equal to or smaller than 1.2 times an upper limit value of the pattern width range.Type: ApplicationFiled: April 24, 2007Publication date: December 27, 2007Applicant: FUJITSU LIMITEDInventors: Shigeki Yoshida, Fumio Ushida, Nobuhisa Naori, Yasutaka Ozaki
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Patent number: 7297558Abstract: A W plug (24) is formed and a W oxidation preventing barrier metal film (25) is formed thereon. After that, an SiON film (27) thinner than the W oxidation preventing barrier metal film (25) is formed and Ar sputter etching is performed on the SiON film (27). As a result, the shape of the surface of the SiON film (27) becomes gentler and deep trenches disappear. Next, an SiON film (28) is formed on the whole surface. A voidless W oxidation preventing insulating film (29) is composed of the SiON (28) film and the SiON film (27).Type: GrantFiled: April 15, 2005Date of Patent: November 20, 2007Assignee: Fujitsu LimitedInventors: Yasutaka Ozaki, Tatsuya Yokota, Nobutaka Ohyagi
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Publication number: 20060273368Abstract: A ferroelectric capacitor is formed above a substrate and made of a lamination of a lower electrode, a capacitor ferroelectric film and an upper electrode stacked in this order. The upper electrode is made of conductive oxide and has such an oxygen concentration distribution as an oxygen concentration in a lower layer region of the upper electrode becomes lower than an oxygen concentration in an upper layer region. An interlayer insulating film covers the ferroelectric capacitor. A via hole is formed through the interlayer insulating film and reaches a position deeper than an upper surface of the upper electrode. The via hole is stopped at a position shallower than a position at which the oxygen concentration of the upper electrode becomes maximum. A conductive member contacts the upper electrode on a bottom of the via hole.Type: ApplicationFiled: December 8, 2005Publication date: December 7, 2006Applicant: FUJITSU LIMITEDInventor: Yasutaka Ozaki
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Publication number: 20060138515Abstract: Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 ?m.Type: ApplicationFiled: December 5, 2005Publication date: June 29, 2006Applicant: FUJITSU LIMITEDInventor: Yasutaka Ozaki
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Publication number: 20060118957Abstract: Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 ?m.Type: ApplicationFiled: March 30, 2005Publication date: June 8, 2006Applicant: FUJITSU LIMITEDInventor: Yasutaka Ozaki
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Publication number: 20050285173Abstract: The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor 44 formed over the first insulation film 26, a first hydrogen diffusion preventing film 48 formed over the first insulation film 26, covering the capacitor 44, a second insulation film 50 formed over the first hydrogen diffusion preventing film and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the first hydrogen diffusion preventing film 26 and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the second insulation film 50, second conductor plug 62 buried in a second contact hole 56 formed down to the lower electrode 38 or the upper electrode 42 of the capacitor 44, a third conductor plug 62 buried in a third contact hole 58 formed down to the first conductor plug 32, and an interconnection 64 connected toType: ApplicationFiled: January 27, 2005Publication date: December 29, 2005Applicant: FUJITSU LIMITEDInventors: Kouichi Nagai, Hideaki Kikuchi, Naoya Sashida, Yasutaka Ozaki
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Publication number: 20050181605Abstract: A W plug (24) is formed and a W oxidation preventing barrier metal film (25) is formed thereon. After that, an SiON film (27) thinner than the W oxidation preventing barrier metal film (25) is formed and Ar sputter etching is performed on the SiON film (27). As a result, the shape of the surface of the SiON film (27) becomes gentler and deep trenches disappear. Next, an SiON film (28) is formed on the whole surface. A voidless W oxidation preventing insulating film (29) is composed of the SiON (28) film and the SiON film (27).Type: ApplicationFiled: April 15, 2005Publication date: August 18, 2005Inventors: Yasutaka Ozaki, Tatsuya Yokota, Nobutaka Ohyagi
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Patent number: 6913970Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.Type: GrantFiled: November 26, 2002Date of Patent: July 5, 2005Assignee: Fujitsu LimitedInventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
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Patent number: 6706540Abstract: There is provided a semiconductor device which includes a capacitor including a lower electrode, a dielectric film, and an upper electrode, a first protection film formed on the capacitor, a first wiring formed on the first protection film, a first insulating film formed on the first wiring, a second wiring formed on the first insulating film, a second insulating film formed on the second wiring, and at least one of a second protection film formed between the first insulating film and the first wiring to cover at least the capacitor and a third protection film formed on the second insulating film to cover the capacitor and set to an earth potential. Accordingly, the degradation of the ferroelectric capacitor formed under the multi-layered wiring structure can be suppressed.Type: GrantFiled: February 11, 2003Date of Patent: March 16, 2004Assignee: Fujitsu LimitedInventors: Yukinobu Hikosaka, Yasutaka Ozaki, Kazuaki Takai