Patents by Inventor Yasutaka Yamashita
Yasutaka Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240168427Abstract: A transport device includes multiple rotation members that rotate, a cycle member that has a loop shape, and that is wound around the multiple rotation members to cycle together with rotation of the rotation members, at least one holding member that is attached to the cycle member, that cycles together with the cycle member, and that holds a leading end portion of a recording medium while being spaced apart from each other in a width direction when the leading end portion arrives at a holding position, and a deformation member that deforms the leading end portion in a thickness direction throughout the width direction by time when the leading end portion arrives at the holding position.Type: ApplicationFiled: May 19, 2023Publication date: May 23, 2024Applicant: FUJIFILM Business Innovation Corp.Inventors: Hideki KUGE, Yoshiki Shimodaira, Masato Yamashita, Takayuki Ukawa, Kazuhiko Arai, Yutaka Kiuchi, Yasutaka Gotoh
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Publication number: 20240162081Abstract: A stacked substrate manufacturing method includes (A) to (D) described below. (A) forming a bonding layer, which includes an oxide layer, on a surface of a first semiconductor substrate. (B) bringing the oxide layer of the bonding layer into contact with a second semiconductor substrate, and bonding the first semiconductor substrate and the second semiconductor substrate with the bonding layer therebetween. (C) forming, after the bonding of the first semiconductor substrate and the second semiconductor substrate, a modification layer with a laser beam on a first division plane along which the first semiconductor substrate is to be divided in a thickness direction thereof. (D) thinning the first semiconductor substrate bonded to the second semiconductor substrate with the bonding layer therebetween by dividing the first semiconductor substrate starting from the modification layer formed at the first division plane.Type: ApplicationFiled: February 25, 2022Publication date: May 16, 2024Inventors: Yohei YAMASHITA, Yasutaka MIZOMOTO, Hayato TANOUE
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Publication number: 20240153822Abstract: A semiconductor chip manufacturing method includes (A) to (E) described below. (A) preparing a stacked substrate including a first semiconductor substrate, a device layer, a separation layer, and a third semiconductor substrate in this order. (B) dicing the first semiconductor substrate, the device layer, and the separation layer. (C) attaching the diced stacked substrate to a tape from an opposite side to the third semiconductor substrate, and mounting the diced stacked substrate to a frame with the tape therebetween. (D) radiating, after mounting the stacked substrate to the frame, a laser beam penetrating the third semiconductor substrate to the separation layer to form a modification layer at an interface between the third semiconductor substrate and the separation layer, or at an inside of the separation layer. (E) separating the third semiconductor substrate and the separation layer starting from the modification layer.Type: ApplicationFiled: February 25, 2022Publication date: May 9, 2024Inventors: Yohei YAMASHITA, Yasutaka MIZOMOTO, Hayato TANOUE
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Publication number: 20240082956Abstract: A substrate processing method includes (A) to (C) to be described below. (A) A substrate having a first main surface and a second main surface opposite to the first main surface, and having unevenness on each of the first main surface and the second main surface is prepared. (B) Based on a measurement result of the unevenness of a first surface between the first main surface and the second main surface of the substrate, the first surface is planarized by radiating a laser beam to the first surface. (C) After planarizing the first surface of the substrate, a second surface of the substrate opposite to the first surface is planarized by grinding the second surface.Type: ApplicationFiled: January 11, 2022Publication date: March 14, 2024Inventors: Susumu HAYAKAWA, Yohei YAMASHITA, Yasutaka MIZOMOTO
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Patent number: 11894822Abstract: A filter device includes: delay units serially connected to delay an input signal and output a delayed signal; multiplication units multiplying the delayed signal by a filter coefficient based on a predetermined value and a multiplying factor adjustment value; a coefficient adjustment unit that, when a multiplication result obtained by multiplying the predetermined value by the multiplying factor adjustment value exceeds a maximum value of a filter-coefficient representation range, divides the multiplication result exceeding the maximum value by the maximum value, and outputs a quotient of division as a coefficient adjustment value; a signal conversion unit outputting a signal obtained by adding after-filter-coefficient-multiplication signals outputted by the multiplication units and an adjusted signal obtained by adjusting a corresponding delayed signal using the coefficient adjustment value; and a division unit generating an output signal by dividing the signal outputted by the signal conversion unit by theType: GrantFiled: April 11, 2022Date of Patent: February 6, 2024Assignee: Mitsubishi Electric CorporationInventors: Yasutaka Yamashita, Shigenori Tani, Kazuma Kaneko, Shigeru Uchida
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Publication number: 20230367552Abstract: A calculation circuit includes: processing circuitry that divides a quantized signal into a first bit string and a second bit string, and converts the first bit string into a sequence including two or more bits and representing a numerical value by a ratio of 1 present therein; calculates the sequence converted by the conversion unit by stochastic signal processing using a combinational circuit; and adds a ratio of 1 present in a sequence after calculation and a value obtained by multiplying the second bit string by a number represented by the first bit string, and performs reconversion into a quantized signal.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Applicant: Mitsubishi Electric CorporationInventors: Shigenori TANI, Yasutaka YAMASHITA
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Patent number: 11765007Abstract: A signal specification identification apparatus includes processing circuitry that estimates the transmission rate of a received signal, performs sampling frequency conversion on the received signal, calculates a probability corresponding to each of a plurality of candidates for a specification of the received signal, selects a candidate using the respective probabilities, and calculates reliability corresponding to a selected candidate, determines whether to output the selected candidate as an identification result or perform the sampling frequency conversion again, based on the reliability, and changes a parameter indicating the ratio of the sampling frequency conversion when it is determined that the sampling frequency conversion is to be performed again. Processing is repeated until the processing circuitry determines that the selected candidate as the identification result is to be output.Type: GrantFiled: January 5, 2023Date of Patent: September 19, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yasutaka Yamashita, Shigeru Uchida
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Publication number: 20230246889Abstract: A modulation scheme identification apparatus includes: a modulation scheme specification circuitry that outputs a first probability distribution for a plurality of modulation schemes for a signal waveform input; a matching rate calculator that calculates a matching rate between the first probability distribution and a second probability distribution defined for a first modulation scheme that is a modulation scheme having a highest probability in the first probability distribution; and a determination circuitry that determines whether the modulation scheme of the signal waveform is the first modulation scheme or an unknown modulation scheme, based on the matching rate.Type: ApplicationFiled: April 11, 2023Publication date: August 3, 2023Applicant: Mitsubishi Electric CorporationInventor: Yasutaka YAMASHITA
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Publication number: 20230155868Abstract: A signal specification identification apparatus includes processing circuitry that estimates the transmission rate of a received signal, performs sampling frequency conversion on the received signal, calculates a probability corresponding to each of a plurality of candidates for a specification of the received signal, selects a candidate using the respective probabilities, and calculates reliability corresponding to a selected candidate, determines whether to output the selected candidate as an identification result or perform the sampling frequency conversion again, based on the reliability, and changes a parameter indicating the ratio of the sampling frequency conversion when it is determined that the sampling frequency conversion is to be performed again. Processing is repeated until the processing circuitry determines that the selected candidate as the identification result is to be output.Type: ApplicationFiled: January 5, 2023Publication date: May 18, 2023Applicant: Mitsubishi Electric CorporationInventors: Yasutaka Yamashita, Shigeru Uchida
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Patent number: 11621736Abstract: A data processing device includes a restoration unit that performs a conversion operation on an input signal to convert the input signal into a signal having no distortion caused by an external factor, and a selection unit that selects and outputs either an unrestored signal, which is the input signal, or a restored signal, which is a signal obtained by the restoration unit by performing the conversion operation, based on a feature quantity of the unrestored signal and on a feature quantity of the restored signal.Type: GrantFiled: February 15, 2022Date of Patent: April 4, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shigenori Tani, Yasutaka Yamashita
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Publication number: 20220239283Abstract: A filter device includes: delay units serially connected to delay an input signal and output a delayed signal; multiplication units multiplying the delayed signal by a filter coefficient based on a predetermined value and a multiplying factor adjustment value; a coefficient adjustment unit that, when a multiplication result obtained by multiplying the predetermined value by the multiplying factor adjustment value exceeds a maximum value of a filter-coefficient representation range, divides the multiplication result exceeding the maximum value by the maximum value, and outputs a quotient of division as a coefficient adjustment value; a signal conversion unit outputting a signal obtained by adding after-filter-coefficient-multiplication signals outputted by the multiplication units and an adjusted signal obtained by adjusting a corresponding delayed signal using the coefficient adjustment value; and a division unit generating an output signal by dividing the signal outputted by the signal conversion unit by theType: ApplicationFiled: April 11, 2022Publication date: July 28, 2022Applicant: Mitsubishi Electric CorporationInventors: Yasutaka YAMASHITA, Shigenori TANI, Kazuma KANEKO, Shigeru UCHIDA
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Patent number: 11381458Abstract: A network management device according to the present invention includes a metric calculation unit that calculates, using location information of multiple nodes constituting a network, metrics for respective combinations of the nodes, a false detection determination unit that determines, using the metrics and using link estimation information, which is information indicating a combination of nodes presumed that has a link therebetween, a falsely detected link corresponding to a combination of nodes indicated as having a link therebetween in the link estimation information, but presumed that has no link therebetween in reality, and a non-detection determination unit that determines, using the metrics and the link estimation information, an undetected link corresponding to a combination of nodes indicated as having no link therebetween in the link estimation information, but presumed that has a link therebetween in reality.Type: GrantFiled: April 13, 2020Date of Patent: July 5, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yasutaka Yamashita, Shigenori Tani, Katsuyuki Motoyoshi
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Publication number: 20220173757Abstract: A data processing device includes a restoration unit that performs a conversion operation on an input signal to convert the input signal into a signal having no distortion caused by an external factor, and a selection unit that selects and outputs either an unrestored signal, which is the input signal, or a restored signal, which is a signal obtained by the restoration unit by performing the conversion operation, based on a feature quantity of the unrestored signal and on a feature quantity of the restored signal.Type: ApplicationFiled: February 15, 2022Publication date: June 2, 2022Applicant: Mitsubishi Electric CorporationInventors: Shigenori TANI, Yasutaka YAMASHITA
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Publication number: 20200244540Abstract: A network management device according to the present invention includes a metric calculation unit that calculates, using location information of multiple nodes constituting a network, metrics for respective combinations of the nodes, a false detection determination unit that determines, using the metrics and using link estimation information, which is information indicating a combination of nodes presumed that has a link therebetween, a falsely detected link corresponding to a combination of nodes indicated as having a link therebetween in the link estimation information, but presumed that has no link therebetween in reality, and a non-detection determination unit that determines, using the metrics and the link estimation information, an undetected link corresponding to a combination of nodes indicated as having no link therebetween in the link estimation information, but presumed that has a link therebetween in reality.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Applicant: Mitsubishi Electric CorporationInventors: Yasutaka YAMASHITA, Shigenori TANI, Katsuyuki MOTOYOSHI
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Patent number: 7394810Abstract: A layer 2 switch enables communication between different layer 2 networks by rewriting an expansion VLAN tag according to a network of a frame transfer destination, as well as producing the same effect, by rewriting an expansion VLAN tag, as that obtained by applying expansion VLAN tags to the third and the following stages.Type: GrantFiled: November 5, 2003Date of Patent: July 1, 2008Assignee: NEC CorporationInventors: Hidefumi Natsume, Yasutaka Yamashita
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Publication number: 20040095941Abstract: A layer 2 switch enables communication between different layer 2 networks by rewriting an expansion VLAN tag according to a network of a frame transfer destination, as well as producing the same effect, by rewriting an expansion VLAN tag, as that obtained by applying expansion VLAN tags to the third and the following stages.Type: ApplicationFiled: November 5, 2003Publication date: May 20, 2004Applicant: NEC CORPORATIONInventors: Hidefumi Natsume, Yasutaka Yamashita