Patents by Inventor Yasuto Igarashi
Yasuto Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150220095Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.Type: ApplicationFiled: April 13, 2015Publication date: August 6, 2015Inventors: Masafumi ONOUCHI, Kazuo OTSUGA, Yasuto IGARASHI, Sadayuki MORITA, Koichiro ISHIBASHI, Kazumasa YANAGISAWA
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Patent number: 9030176Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.Type: GrantFiled: November 12, 2012Date of Patent: May 12, 2015Assignee: Renesas Electronics CorporationInventors: Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa
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Patent number: 8730703Abstract: Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.Type: GrantFiled: January 24, 2013Date of Patent: May 20, 2014Assignee: Renesas Electronics CorporationInventors: Kazuki Fukuoka, Yasuto Igarashi, Ryo Mori, Yoshihiko Yasu, Toshio Sasaki
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Patent number: 8482038Abstract: A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.Type: GrantFiled: July 10, 2012Date of Patent: July 9, 2013Assignee: Renesas Electronics CorporationInventors: Takayuki Sasaki, Yasuto Igarashi, Naozumi Morino
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Patent number: 8379425Abstract: Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.Type: GrantFiled: February 26, 2010Date of Patent: February 19, 2013Assignee: Renesas Electronics CorporationInventors: Kazuki Fukuoka, Yasuto Igarashi, Ryo Mori, Yoshihiko Yasu, Toshio Sasaki
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Publication number: 20120280741Abstract: A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.Type: ApplicationFiled: July 10, 2012Publication date: November 8, 2012Inventors: Takayuki SASAKI, Yasuto Igarashi, Naozumi Morino
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Patent number: 8242541Abstract: A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.Type: GrantFiled: January 9, 2007Date of Patent: August 14, 2012Assignee: Renesas Electronics CorporationInventors: Takayuki Sasaki, Yasuto Igarashi, Naozumi Morino
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Publication number: 20110068826Abstract: A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed.Type: ApplicationFiled: December 1, 2010Publication date: March 24, 2011Inventors: Yuri AZUMA, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
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Patent number: 7855593Abstract: A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed.Type: GrantFiled: July 6, 2009Date of Patent: December 21, 2010Assignee: Renesas Electronics CorporationInventors: Yuri Azuma, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
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Publication number: 20100219800Abstract: Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.Type: ApplicationFiled: February 26, 2010Publication date: September 2, 2010Inventors: Kazuki FUKUOKA, Yasuto Igarashi, Ryo Mori, Yoshihiko Yasu, Toshio Sasaki
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Publication number: 20090267686Abstract: A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed.Type: ApplicationFiled: July 6, 2009Publication date: October 29, 2009Inventors: Yuri Azuma, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
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Publication number: 20080218224Abstract: The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.Type: ApplicationFiled: May 13, 2008Publication date: September 11, 2008Inventors: Naozumi Morino, Takahiro Irita, Yasuto Igarashi
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Patent number: 7411267Abstract: The invention provides a semiconductor integrated circuit device with improved designing efficiency while achieving higher functions. An inner circuit is surrounded by a plurality of cells in which a first switch element for connecting a power supply voltage line or a ground voltage supply line to a power supply line of an internal circuit is disposed below power supply lines extending in a first and second directions, and the power lines are connected together.Type: GrantFiled: February 3, 2005Date of Patent: August 12, 2008Assignee: Renesas Technology Corp.Inventors: Kentaro Yamawaki, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
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Patent number: 7378887Abstract: The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.Type: GrantFiled: July 31, 2006Date of Patent: May 27, 2008Assignee: Renesas Technology Corp.Inventors: Naozumi Morino, Takahiro Irita, Yasuto Igarashi
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Publication number: 20070206781Abstract: A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.Type: ApplicationFiled: January 9, 2007Publication date: September 6, 2007Inventors: Takayuki Sasaki, Yasuto Igarashi, Naozumi Morino
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Publication number: 20070046342Abstract: The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.Type: ApplicationFiled: July 31, 2006Publication date: March 1, 2007Inventors: Naozumi Morino, Takahiro Irita, Yasuto Igarashi
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Publication number: 20050232053Abstract: A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided.Type: ApplicationFiled: April 20, 2005Publication date: October 20, 2005Inventors: Yuri Azuma, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
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Publication number: 20050218959Abstract: The invention provides a semiconductor integrated circuit device with improved designing efficiency while achieving higher functions.Type: ApplicationFiled: February 3, 2005Publication date: October 6, 2005Inventors: Kentaro Yamawaki, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
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Patent number: 6301184Abstract: A DRAM module is applied to the system LSI which is provided with a standby mode for suppressing the whole operation thereof and an operation standby mode which permits at least the DRAM module to operate but suppresses the operation of other circuits. The above-mentioned modes as well as a substrate bias control technology are applied to the CMOS system LSI that operates on a low voltage. The system LSI is controlled to hold or not to hold data, enabling a memory of a large capacity to be mounted and consuming a sufficiently decreased amount of electric power.Type: GrantFiled: January 11, 2000Date of Patent: October 9, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Toshio Sasaki, Yoshihiko Yasu, Kazumasa Yanagisawa, Yuji Tanaka, Toshiaki Takahira, Yasuto Igarashi, Mariko Ohtsuka, Yasunobu Aoki