Patents by Inventor Yasutoshi Kurihara

Yasutoshi Kurihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7141741
    Abstract: A semiconductor device in which electrodes of a plurality of semiconductor elements are bonded onto at least one of a plurality of electrode patterns on an insulator substrate, the other surface of the insulator substrate being bonded to a heat dissipating base. The upper surface of the heat dissipating base is covered with a member for cutting off the semiconductor elements from the outer environment. Terminals electrically connect the electrodes on said insulator substrate and the electrode placed outside the cutoff member. The material of the heat dissipating base has a linear expanding coefficient larger than that of the semiconductor element and smaller than three times that of the semiconductor element, and a thermal conductivity larger than 100 W/mK. The semiconductor elements are arranged on at least one electrode surface and in at least two regions divided by the other electrode surface on the insulator substrate.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: November 28, 2006
    Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.
    Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
  • Publication number: 20050029666
    Abstract: A semiconductor device, in which a solder layer bonding chip parts and wiring members are enclosed with the resin layer, and the solder layer is comprised of a compound body in which metal powder is distributed in the matrix metal, is disclosed. When a semiconductor device in which the chip parts are installed in the wiring member with the solders, the soldering part is sealed with the resin is mounted secondly on the external wiring member, the outflow of the solders and the short circuit due to the outflow, the disconnections, and the displacement of the chip parts can be prevented.
    Type: Application
    Filed: August 27, 2002
    Publication date: February 10, 2005
    Inventors: Yasutoshi Kurihara, Yoshimasa Takahashi, Tsuneo Endoh, Mikio Negishi, Masashi Yamaura, Hirokazu Nakajima, Yosuke Sakurai, Hironori Kodama
  • Publication number: 20040056349
    Abstract: A semiconductor device in which electrodes of a plurality of semiconductor elements are bonded onto at least one of a plurality of electrode patterns on an insulator substrate, the other surface of the insulator substrate being bonded to a heat dissipating base. The upper surface of the heat dissipating base is covered with a member for cutting off the semiconductor elements from the outer environment. Terminals electrically connect the electrodes on said insulator substrate and the electrode placed outside the cutoff member. The material of the heat dissipating base has a linear expanding coefficient larger than that of the semiconductor element and smaller than three times that of the semiconductor element, and a thermal conductivity larger than 100 W/mK. The semiconductor elements are arranged on at least one electrode surface and in at least two regions divided by the other electrode surface on the insulator substrate.
    Type: Application
    Filed: September 22, 2003
    Publication date: March 25, 2004
    Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
  • Patent number: 6710263
    Abstract: In a semiconductor device, the likely occurrence of cracking of a ceramic substrate, and the consequential disconnection of internal layer wiring, due to thermal changes suffered when the semiconductor device is mounted on external wiring boards having different thermal expansion is prevented. The semiconductor device has a ceramic substrate, a wiring pattern formed on a first principal plane and having mounted semiconductor components, an external electrode portion formed on a second principal plane and connected to an external circuit, internal layer wiring formed inside said ceramic substrate to electrically connect said wiring pattern and said external electrode portion via through-hole wiring, and semiconductor components and a resin layer covering said semiconductor components, wherein the internal layer wiring is formed internally with respect to the side of said ceramic substrate with a clearance of at least 0.05 mm.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: March 23, 2004
    Assignees: Renesas Technology Corporation, Hitachi Tohbu Semiconductors, Ltd.
    Inventors: Toshiyuki Kobayashi, Yasutoshi Kurihara, Takumi Ueno, Nobuyoshi Maejima, Hirokazu Nakajima, Tomio Yamada, Tsuneo Endoh
  • Publication number: 20030201530
    Abstract: To provide a composite material member for semiconductor device, an insulated semiconductor device and non-insulated semiconductor device using the composite material member, which are effective for obtaining a semiconductor device that alleviates thermal stress or thermal strain occurring during production or operation, has no possibilities of deformation, degeneration and rupture of each member, and is highly reliably and inexpensive. The composite material member for semiconductor device is characterized by being a composite metal plate with particles composed of cuprous oxide dispersed in a copper matrix, in which a surface of the composite metal plate is covered with a metal layer, and a copper layer with thickness of 0.5 &mgr;m or larger exists in an interface formed by the composite metal plate and the metal layer.
    Type: Application
    Filed: May 5, 2003
    Publication date: October 30, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yasutoshi Kurihara, Yasuo Kondo, Takumi Ueno, Toshiaki Morita, Kenji Koyama, Takashi Suzumura, Kazuhiko Nakagawa, Kunihiro Fukuda
  • Patent number: 6579623
    Abstract: To provide a composite material member for semiconductor device, an insulated semiconductor device and non-insulated semiconductor device using the composite material member, which are effective for obtaining a semiconductor device that alleviates thermal stress or thermal strain occurring during production or operation, has no possibilities of deformation, degeneration and rupture of each member, and is highly reliably and inexpensive. The composite material member for semiconductor device is characterized by being a composite metal plate with particles composed of cuprous oxide dispersed in a copper matrix, in which a surface of the composite metal plate is covered with a metal layer, and a copper layer with thickness of 0.5 &mgr;m or larger exists in an interface formed by the composite metal plate and the metal layer.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: June 17, 2003
    Assignees: Hitachi, Ltd., Hitachi Cable, Ltd.
    Inventors: Yasutoshi Kurihara, Yasuo Kondo, Takumi Ueno, Toshiaki Morita, Kenji Koyama, Takashi Suzumura, Kazuhiko Nakagawa, Kunihiro Fukuda
  • Publication number: 20030016502
    Abstract: A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of the semiconductor element being electrically connected to the electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of the heat dissipating base being covered with a member for cutting off the semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside the cutoff member being provided, wherein the material of the heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK, the semiconductor elements being
    Type: Application
    Filed: March 20, 2002
    Publication date: January 23, 2003
    Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
  • Publication number: 20020192488
    Abstract: To provide a composite material member for semiconductor device, an insulated semiconductor device and non-insulated semiconductor device using the composite material member, which are effective for obtaining a semiconductor device that alleviates thermal stress or thermal strain occurring during production or operation, has no possibilities of deformation, degeneration and rupture of each member, and is highly reliably and inexpensive. The composite material member for semiconductor device is characterized by being a composite metal plate with particles composed of cuprous oxide dispersed in a copper matrix, in which a surface of the composite metal plate is covered with a metal layer, and a copper layer with thickness of 0.5 &mgr;m or larger exists in an interface formed by the composite metal plate and the metal layer.
    Type: Application
    Filed: February 27, 2002
    Publication date: December 19, 2002
    Inventors: Yasutoshi Kurihara, Yasuo Kondo, Takumi Ueno, Toshiaki Morita, Kenji Koyama, Takashi Suzumura, Kazuhiko Nakagawa, Kunihiro Fukuda
  • Patent number: 6434008
    Abstract: A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of the semiconductor element being electrically connected to the electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of the heat dissipating base being covered with a member for cutting off the semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside the cutoff member being provided, wherein the material of the heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK, the semiconductor elements being
    Type: Grant
    Filed: August 27, 1998
    Date of Patent: August 13, 2002
    Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.
    Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
  • Patent number: 6353258
    Abstract: A semiconductor module has a plurality of power semiconductor devices mounted on a substrate, and a metal foil for wiring is mounted on the substrate so that an asymmetric unit arrangement of the semiconductor devices is formed. In the device, all of the units are arranged in the same direction on the substrate, and all of the units are electrically connected with electrode terminal feet, and the electrode terminal feet are electrically connected with linkage terminal foot. The electrode terminal feet are disposed with a certain interval.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: March 5, 2002
    Assignees: Hitachi, Ltd., Hitachi Car Engineering Co., Ltd.
    Inventors: Hirokazu Inoue, Ryuichi Saito, Mutsuhiro Mori, Yasutoshi Kurihara, Jin Onuki, Shin Kimura, Satoshi Shimada, Kazuhiro Suzuki, Yukio Kamita, Isao Kobayashi, Kazuji Yamada, Naohiro Momma
  • Publication number: 20010023983
    Abstract: Supply of a semiconductor device capable of preventing the likely occurrence of cracking of a ceramic substrate, and the consequential disconnection of internal layer wiring, due to the thermal changes suffered when the semiconductor device is mounted on external wiring boards different in thermal expansion coefficient.
    Type: Application
    Filed: February 23, 2001
    Publication date: September 27, 2001
    Inventors: Toshiyuki Kobayashi, Yasutoshi Kurihara, Takumi Ueno, Nobuyoshi Maejima, Hirokazu Nakajima, Tomio Yamada, Tsuneo Endoh
  • Patent number: 5956231
    Abstract: A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of the semiconductor element being electrically connected to the electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of the heat dissipating base being covered with a member for cutting off the semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside the cutoff member being provided, wherein the material of the heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK, the semiconductor elements being
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: September 21, 1999
    Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.
    Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
  • Patent number: 4649990
    Abstract: A heat-conducting cooling module for cooling a semiconductor substrate in an integrated circuit package assembly in which a semiconductor substrate is mounted on a base board by small solder pellets, and which contains a single substrate or laminated substrates. A heat-conducting relay member is provided between the semiconductor substrate and a housing so as to be pressed onto the semiconductor substrate. At least either one of the housing or the heat-conducting relay member is made of a sintered product which includes silicon carbide as a chief component.
    Type: Grant
    Filed: May 6, 1985
    Date of Patent: March 17, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Yasutoshi Kurihara, Tasao Soga, Hiroaki Hachino, Kenji Miyata, Masahiro Okamura, Fumiyuki Kobayashi, Takahiro Daikoku
  • Patent number: 4556899
    Abstract: In an insulated type semiconductor device, a metal member is disposed between an insulating member and a circuit element which includes a semiconductor substrate. The metal member is a composite metal member having at least two different kinds of metal layers bonded to each other. In a preferred embodiment, in order to reduce undesirable effects caused by differences in the thermal coefficients .alpha..sub.I and .alpha..sub.S of the insulating member and the semiconductor substrate, respectively, the thermal expansion coefficient of said composite metal member as a whole .alpha..sub.M is adjusted in a range between .alpha..sub.I and .alpha..sub.S.
    Type: Grant
    Filed: June 7, 1982
    Date of Patent: December 3, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Yasutoshi Kurihara, Yoshihiro Suzuki, Michio Ooue, Hiroaki Hachino, Mitsuo Yanagi
  • Patent number: 4352120
    Abstract: In a semiconductor device, an active element is mounted on a supporter made of silicon carbide SiC. Since the thermal expansion coefficient of SiC is nearly equal to that of the semiconductor element, the integration of the element and the supporter will not give rise to thermal stresses in the element. Since silicon carbide has high degrees of thermal dissipation and conduction, the supporter of SiC can effectively dissipate heat generated in the semiconductor element. And since SiC has a high electrical conductivity and a high mechanical strength and is also light, it can be used as electrodes for the semiconductor element.
    Type: Grant
    Filed: April 22, 1980
    Date of Patent: September 28, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Yasutoshi Kurihara, Hiroaki Hachino, Kousuke Nakamura
  • Patent number: 4151502
    Abstract: A semiconductor transducer comprises a semiconductor strain gauge composed of a mono-crystalline semiconducting material and a strain sensing region formed in a first main surface of the mono-crystalline semiconducting material, and a strain measuring member coupled to the semiconductor strain gauge through an alloy material. An electrical insulating layer is attached to a second main surface of the mono-crystalline semiconducting material which is coupled to the strain measuring member through the alloy material. The insulating layer is extended to a side surface of the mono-crystalline semiconducting material thereby to cover the same side.
    Type: Grant
    Filed: April 15, 1977
    Date of Patent: April 24, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Yasutoshi Kurihara, Tetuo Kosugi, Teruyuki Kagami, Satoshi Shimada, Yasumasa Matsuda, Kazuji Yamada
  • Patent number: 4143385
    Abstract: A photocoupler wherein a semiconductor photo-responsive element and a semiconductor light emitting element are arranged on an insulating substrate in such a mannner that they oppose each other with a P-N junction of the latter being perpendicular to a light receiving face of the former. At least one of the elements is connected with electric wiring on the insulating substrate by the use of a brazing material at three or more points which lie on an identical plane of the insulating substrate but do not lie on one straight line.
    Type: Grant
    Filed: September 29, 1977
    Date of Patent: March 6, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Tadahiko Miyoshi, Yasutoshi Kurihara
  • Patent number: 4058821
    Abstract: A photo-coupler semiconductor device includes a semiconductor light emitter and a semiconductor light detector coupled optically with each other through an optical guide. A portion of the optical guide close to the semiconductor light detector is made of glass. The glass portion of the optical guide is brought into intimate contact with a glass layer which is formed on a light sensitive region of the semiconductor light detector. The intimate contact is made by melting the glass portion on the glass layer.
    Type: Grant
    Filed: March 19, 1976
    Date of Patent: November 15, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Tadahiko Miyoshi, Yasutoshi Kurihara, Tatsuya Kamei, Takuzo Ogawa
  • Patent number: 4008485
    Abstract: A gallium arsenide infrared-light emitting diode in which an Si-doped p-type GaAs layer is formed on an Si-doped n-type GaAs layer which is performed on an n-type GaAs substrate doped with at least one selected from Sn, Se, Te and S.
    Type: Grant
    Filed: June 20, 1975
    Date of Patent: February 15, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Tadahiko Miyoshi, Yasutoshi Kurihara, Mitsuru Ura
  • Patent number: 4001859
    Abstract: A photo coupler comprises a multilayer insulating substrate having a cavity on a predetermined portion and a first conductive layer at the bottom of the cavity and a second conductive layer on one surface of the insulating substrate. A light emitting diode is disposed in the cavity with a substantial light emitting zone thereof being in the cavity and is electrically connected to the first conductive layer. A photo responsive device is placed above the cavity on the substrate with the photo sensitive surface of the device facing the light emitting diode and being electrically connected to the second conductive layer.
    Type: Grant
    Filed: January 26, 1976
    Date of Patent: January 4, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Tadahiko Miyoshi, Yasutoshi Kurihara