Patents by Inventor Yasutoshi Takizawa

Yasutoshi Takizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8595010
    Abstract: A program for generating Hidden Markov Models to be used for speech recognition with a given speech recognition system, the information storage medium storing a program, that renders a computer to function as a scheduled-to-be-used model group storage section that stores a scheduled-to-be-used model group including a plurality of Hidden Markov Models scheduled to be used by the given speech recognition system, and a filler model generation section that generates Hidden Markov Models to be used as filler models by the given speech recognition system based on all or at least a part of the Hidden Markov Model group in the scheduled-to-be-used model group.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: November 26, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Paul W. Shields, Matthew E. Dunnachie, Yasutoshi Takizawa
  • Publication number: 20100217593
    Abstract: A program for generating Hidden Markov Models to be used for speech recognition with a given speech recognition system, the information storage medium storing a program, that renders a computer to function as a scheduled-to-be-used model group storage section that stores a scheduled-to-be-used model group including a plurality of Hidden Markov Models scheduled to be used by the given speech recognition system, and a filler model generation section that generates Hidden Markov Models to be used as filler models by the given speech recognition system based on all or at least a part of the Hidden Markov Model group in the scheduled-to-be-used model group.
    Type: Application
    Filed: February 5, 2010
    Publication date: August 26, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Paul W. Shields, Matthew E. Dunnachie, Yasutoshi Takizawa
  • Patent number: 5739596
    Abstract: An electronic apparatus comprises a main circuit having a main CPU and a power supply system which includes plural main batteries for supplying operating power to said main circuit, a back-up battery, a switching circuit connected between each main battery and the main circuit, power means for enabling the operation of the main circuit, a charge detector for detecting the charging level of each main battery, and power controller responsive to the power means and the charge detector and having a sub-CPU for individually controlling the switching circuit according to either a single connection mode or a multiple connection mode. In the single connection mode only one of the main batteries is connected to said main circuit. In the multiple connection mode, at least two main batteries, each in series with a respective diode means, are connected in parallel to the main circuit.
    Type: Grant
    Filed: April 5, 1996
    Date of Patent: April 14, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Yasutoshi Takizawa, Katsunori Nagao, Shigeo Ikeda