Patents by Inventor Yasuyoshi Mishima
Yasuyoshi Mishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8470653Abstract: A method for manufacturing a P-type MOS transistor includes forming a gate insulating film on the substrate, forming a gate electrode from amorphous silicon containing no impurities on the gate insulating film, performing a heat treatment for controlling the film characteristics of the amorphous silicon, depositing a nickel (Ni) layer on the gate electrode, and forming nickel silicides from the gate electrode and the nickel (Ni).Type: GrantFiled: August 14, 2009Date of Patent: June 25, 2013Assignee: Fujitsu LimitedInventors: Teruo Kurahashi, Yasuyoshi Mishima, Yukie Sakita
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Patent number: 7968466Abstract: A method for fabricating an electron device on a substrate includes the steps of forming a dummy film over the substrate such that the dummy film covers a device region of the substrate and an outer region of the substrate outside the device region, forming a dummy pattern by patterning the dummy film such that the dummy pattern has a first height in the device region and a second height smaller than the first height in the outer region, forming another film over the substrate such that the film covers the dummy pattern in the device region and in the outer region with a shape conformal to a cross-sectional shape of the dummy pattern, and applying an anisotropic etching process acting generally perpendicularly to the substrate such that a surface of the substrate is exposed in the device region and in the outer region.Type: GrantFiled: November 27, 2007Date of Patent: June 28, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Kenji Ishikawa, Hideharu Shido, Takeo Nagata, Teruo Kurahashi, Yasuyoshi Mishima
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Patent number: 7947547Abstract: A semiconductor device fabrication method by which CMOS transistors with low-resistance metal gate electrodes each having a proper work function can be fabricated. A HfN layer in which nitrogen concentration in an nMOS transistor formation region differs from nitrogen concentration in a pMOS transistor formation region is formed. A MoN layer is formed over the HfN layer and heat treatment is performed. Nitrogen diffuses from the MoN layer into the HfN layer in which nitrogen concentration is low and a work function is set by the HfN layer according to nitrogen concentration which depends on the nitrogen content of the HfN layer before the heat treatment and the amount of nitrogen that diffuses into the HfN layer. On the other hand, nitrogen hardly diffuses from the MoN layer into the HfN layer which originally has a certain nitrogen content, and a work function is set by the HfN layer according to nitrogen concentration in the HfN layer before the heat treatment.Type: GrantFiled: June 12, 2008Date of Patent: May 24, 2011Assignee: Fujitsu LimitedInventors: Teruo Kurahashi, Manabu Sakamoto, Yasuyoshi Mishima
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Patent number: 7943500Abstract: The method of manufacturing a semiconductor device comprises; forming an HfSiO film 36 on a silicon substrate 26; exposing the HfSiO film 36 to NH3 gas to thereby form an HfSiON film 38; forming an HfSiO film 40 on the HfSiON film 38; adhering Al to the surface of the HfSiO film 40 to thereby form an Al adhered layer 58 on the surface of the HfSiO film 40; and forming a polysilicon film 42 on the HfSiO film 40 with the Al adhered layer 58 formed on the surface.Type: GrantFiled: September 29, 2008Date of Patent: May 17, 2011Assignee: Fujitsu LimitedInventors: Masaomi Yamaguchi, Yasuyoshi Mishima
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Patent number: 7910415Abstract: A method of manufacturing a semiconductor device including a substrate; an insulating film formed thereon; a first semiconductor layer where strain is induced in the directions parallel to the surface of the substrate, the first semiconductor layer being on the insulating film; a source region and a drain region formed in the first semiconductor layer; and a gate layered body formed of a gate insulating film and a gate electrode on the first semiconductor layer is disclosed. The method includes the steps of (a) forming a second semiconductor layer by epitaxial growth on the first semiconductor layer; (b) heating the second semiconductor layer; and (c) removing the second semiconductor layer. The second semiconductor layer is different in lattice constant in an in-plane direction from the first semiconductor layer. Step (b) induces the strain in the first semiconductor layer by exposing the surface of the second semiconductor layer to energy lines.Type: GrantFiled: October 25, 2006Date of Patent: March 22, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Yasuyoshi Mishima
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Publication number: 20100044799Abstract: A method for manufacturing a P-type MOS transistor includes forming a gate insulating film on the substrate, forming a gate electrode from amorphous silicon containing no impurities on the gate insulating film, performing a heat treatment for controlling the film characteristics of the amorphous silicon, depositing a nickel (Ni) layer on the gate electrode, and forming nickel silicides from the gate electrode and the nickel (Ni).Type: ApplicationFiled: August 14, 2009Publication date: February 25, 2010Applicant: FUJITSU LIMITEDInventors: Teruo Kurahashi, Yasuyoshi Mishima, Yukie Sakita
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Patent number: 7612400Abstract: An MIM device includes a lower electrode of a metal nitride film, a hysteresis film of an oxide film containing Nb formed on the lower electrode, and an upper electrode of a metal nitride film formed on the hysteresis film.Type: GrantFiled: November 26, 2007Date of Patent: November 3, 2009Assignee: Fujitsu LimitedInventors: Teruo Kurahashi, Hideharu Shido, Kenji Ishikawa, Takeo Nagata, Yasuyoshi Mishima, Yukie Sakita
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Publication number: 20090057739Abstract: The Ge channel device comprises: a Ge channel layer (2); a Si-containing interface layer (4) formed on the Ge channel layer (2); a La2O3 layer (6) formed on the interface layer (4); and an electrically conductive layer (8) formed on the La2O3 layer (6). In this device, the Si-containing interface layer (4) functions to suppress the diffusion of Ge atoms into the La2O3 layer (6) and thereby prevents the formation of Ge oxide in the La2O3 layer (6); accordingly, a Ge channel device whose C-V characteristic exhibits only a small hysteresis can be achieved.Type: ApplicationFiled: August 28, 2008Publication date: March 5, 2009Applicant: Tokyo Institute of TechnologyInventors: Hiroshi Iwai, Takeo Hattori, Kazuo Tsutsui, Kuniyuki Kakushima, Parhat Ahmet, Jaeyeol Song, Masaki Yoshimaru, Yasuyoshi Mishima, Tomonori Aoyama, Hiroshi Oji, Yoshitake Kato
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Publication number: 20090039391Abstract: On an insulation layer 12 formed on a silicon substrate 10, there are formed in an NMOS transistor region 16 an NMOS transistor 14 comprising a silicon layer 34, a lattice-relaxed silicon germanium layer 22 formed on the silicon layer 34, a tensile-strained silicon layer 24 formed on the silicon germanium layer 22 and a gate electrode 28 formed on the silicon layer 24 with a gate insulation film 26 formed therebetween and in a PMOS transistor region 20 a PMOS transistor 18 comprising a silicon layer 34, a compression-strained silicon germanium layer formed on the silicon layer 34 and a gate electrode 28 formed on the silicon germanium layer 36 with a gate insulation film 26 formed therebetween.Type: ApplicationFiled: October 1, 2008Publication date: February 12, 2009Applicant: Fujitsu LimitedInventors: Hirosato Ochimizu, Yasuyoshi Mishima
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Publication number: 20090026557Abstract: The method of manufacturing a semiconductor device comprises; forming an HfSiO film 36 on a silicon substrate 26; exposing the HfSiO film 36 to NH3 gas to thereby form an HfSiON film 38; forming an HfSiO film 40 on the HfSiON film 38; adhering Al to the surface of the HfSiO film 40 to thereby form an Al adhered layer 58 on the surface of the HfSiO film 40; and forming a polysilicon film 42 on the HfSiO film 40 with the Al adhered layer 58 formed on the surface.Type: ApplicationFiled: September 29, 2008Publication date: January 29, 2009Applicant: FUJITSU LIMITEDInventors: Masaomi YAMAGUCHI, Yasuyoshi MISHIMA
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Publication number: 20090008724Abstract: The semiconductor device according to the present invention comprises a gate insulating film 16 formed on a silicon substrate 10 and including a silicon oxide film 12 and a Hf-based high dielectric constant insulating film 14 doped with Al; a gate electrode 18 of a polysilicon film formed on the gate insulating film 16; and a sidewall insulating film 20 formed on the side walls of the gate electrode 18 and the Hf-based high dielectric constant insulating film 14, and the maximum value of the depth-wise concentration distribution of the Al doped in the Hf-based high dielectric constant insulating film 14 is 1×1021-4×1021 atoms/cm3.Type: ApplicationFiled: August 6, 2008Publication date: January 8, 2009Applicant: Fujitsu LimitedInventors: Yasuyoshi MISHIMA, Masaomi YAMAGUCHI
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Patent number: 7449379Abstract: On an insulation layer 12 formed on a silicon substrate 10, there are formed in an NMOS transistor region 16 an NMOS transistor 14 comprising a silicon layer 34, a lattice-relaxed silicon germanium layer 22 formed on the silicon layer 34, a tensile-strained silicon layer 24 formed on the silicon germanium layer 22 and a gate electrode 28 formed on the silicon layer 24 with a gate insulation film 26 formed therebetween and in a PMOS transistor region 20 a PMOS transistor 18 comprising a silicon layer 34, a compression-strained silicon germanium layer formed on the silicon layer 34 and a gate electrode 28 formed on the silicon germanium layer 36 with a gate insulation film 26 formed therebetween.Type: GrantFiled: November 14, 2005Date of Patent: November 11, 2008Assignee: Fujitsu LimitedInventors: Hirosato Ochimizu, Yasuyoshi Mishima
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Publication number: 20080242068Abstract: A semiconductor device fabrication method by which CMOS transistors with low-resistance metal gate electrodes each having a proper work function can be fabricated. A HfN layer in which nitrogen concentration in an nMOS transistor formation region differs from nitrogen concentration in a pMOS transistor formation region is formed. A MoN layer is formed over the HfN layer and heat treatment is performed. Nitrogen diffuses from the MoN layer into the HfN layer in which nitrogen concentration is low and a work function is set by the HfN layer according to nitrogen concentration which depends on the nitrogen content of the HfN layer before the heat treatment and the amount of nitrogen that diffuses into the HfN layer. On the other hand, nitrogen hardly diffuses from the MoN layer into the HfN layer which originally has a certain nitrogen content, and a work function is set by the HfN layer according to nitrogen concentration in the HfN layer before the heat treatment.Type: ApplicationFiled: June 12, 2008Publication date: October 2, 2008Applicant: FUJITSU LIMITEDInventors: Teruo KURAHASHI, Manabu SAKAMOTO, Yasuyoshi MISHIMA
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Patent number: 7399662Abstract: A method of making a thin film transistor device, including forming and patterning a semiconductor film to form first and second semiconductor films in, respectively, low-voltage driven and high-voltage driven thin film transistor formation regions. The method also includes forming a first insulating film on the first and second semiconductor films, and forming a first gate electrode on the first insulating film in the low-voltage driven thin film transistor formation region. Additionally, a second insulating film is formed on the entire surface of the resultant structure above the substrate, and a second gate electrode is formed on the second insulating film in the high-voltage driven thin film transistor formation region. The method also includes etching the first and second insulating films, thus forming first and second gate insulating films below, respectively, the first and second gate electrodes, with the second gate insulating film being wider than the second gate electrode.Type: GrantFiled: October 7, 2005Date of Patent: July 15, 2008Assignee: Sharp Kabushiki KaishaInventors: Ken-ichi Yanai, Yoshio Nagahiro, Kazushige Hotta, Koji Ohgata, Yasuyoshi Mishima, Nobuo Sasaki
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Publication number: 20080124933Abstract: A method for fabricating an electron device on a substrate includes the steps of forming a dummy film over the substrate such that the dummy film covers a device region of the substrate and an outer region of the substrate outside the device region, forming a dummy pattern by patterning the dummy film such that the dummy patter has a first height in the device region and a second height smaller than the first height in the outer region, forming another film over the substrate such that the film covers the dummy pattern in the device region and in the outer region with a shape conformal to a cross-sectional shape of the dummy pattern, and applying an anisotropic etching process acting generally perpendicularly to the substrate such that a surface of the substrate is exposed in the device region and in the outer region.Type: ApplicationFiled: November 27, 2007Publication date: May 29, 2008Applicant: FUJITSU LIMITEDInventors: Kenji Ishikawa, Hideharu Shido, Takeo Nagata, Teruo Kurahashi, Yasuyoshi Mishima
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Publication number: 20080121858Abstract: An MIM device includes a lower electrode of a metal nitride film, a hysteresis film of an oxide film containing Nb formed on the lower electrode, and an upper electrode of a metal nitride film formed on the hysteresis film.Type: ApplicationFiled: November 26, 2007Publication date: May 29, 2008Applicant: FUJITSU LIMITEDInventors: Teruo KURAHASHI, Hideharu SHIDO, Kenji ISHIKAWA, Takeo NAGATA, Yasuyoshi MISHIMA, Yukie SAKITA
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Publication number: 20070059875Abstract: A method of manufacturing a semiconductor device including a substrate; an insulating film formed thereon; a first semiconductor layer where strain is induced in the directions parallel to the surface of the substrate, the first semiconductor layer being on the insulating film; a source region and a drain region formed in the first semiconductor layer; and a gate layered body formed of a gate insulating film and a gate electrode on the first semiconductor layer is disclosed. The method includes the steps of (a) forming a second semiconductor layer by epitaxial growth on the first semiconductor layer; (b) heating the second semiconductor layer; and (c) removing the second semiconductor layer. The second semiconductor layer is different in lattice constant in an in-plane direction from the first semiconductor layer. Step (b) induces the strain in the first semiconductor layer by exposing the surface of the second semiconductor layer to energy lines.Type: ApplicationFiled: October 25, 2006Publication date: March 15, 2007Applicant: FUJITSU LIMITEDInventor: Yasuyoshi Mishima
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Publication number: 20060208318Abstract: A high-performance CMOS field effect semiconductor device using metal gate electrodes. An n-type gate electrode and a p-type gate electrode are formed by using a same metal and differ in nitrogen concentration. As a result, a high-performance CMOS field effect semiconductor device having the n-type gate electrode and the p-type gate electrode between which a work function difference is a predetermined value can be realized. By forming a low-resistance layer on layers which are formed by using the same metal and which differ in nitrogen concentration, it is possible to reduce the resistance of the n-type gate electrode and the p-type gate electrode while controlling the work functions of the n-type gate electrode and the p-type gate electrode. Therefore, a higher-performance CMOS field effect semiconductor device can be realized.Type: ApplicationFiled: March 9, 2006Publication date: September 21, 2006Applicant: FUJITSU LIMITEDInventors: Manabu Sakamoto, Teruo Kurahashi, Yasuyoshi Mishima
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Patent number: 7038283Abstract: In a case of a liquid crystal display apparatus, a gate insulating film of a TFT driven at a low voltage (3.3 V or 5 V) is constituted by one insulating film, and a thickness thereof is set to, for example, 30 nm. This TFT has a structure in which LDD regions (low concentration impurity regions) are not provided. A TFT having a CMOS structure, which is driven at a high voltage (18 V), has a gate insulating film constituted by two insulating films having a thickness of, for example, 130 nm in total. In an n-type TFT, a low concentration impurity region is provided on a drain side. A p-type TFT has a structure having no LDD region. A pixel TFT has a gate insulating film constituted by two insulating films, and LDD regions provided in both of its source/drain.Type: GrantFiled: March 22, 2002Date of Patent: May 2, 2006Assignee: Fujitsu Display Technologies CorporationInventors: Kenichi Yanai, Yoshio Nagahiro, Kazushige Hotta, Koji Ohgata, Yasuyoshi Mishima, Nobuo Sasaki
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Publication number: 20060081946Abstract: In a case of a liquid crystal display apparatus, a gate insulating film of a TFT driven at a low voltage (3.3 V or 5 V) is constituted by one insulating film, and a thickness thereof is set to, for example, 30 nm. This TFT has a structure in which LDD regions (low concentration impurity regions) are not provided. A TFT having a CMOS structure, which is driven at a high voltage (18 V), has a gate insulating film constituted by two insulating films having a thickness of, for example, 130 nm in total. In an n-type TFT, a low concentration impurity region is provided on a drain side. A p-type TFT has a structure having no LDD region. A pixel TFT has a gate insulating film constituted by two insulating films, and LDD regions provided in both of its source/drain.Type: ApplicationFiled: October 7, 2005Publication date: April 20, 2006Applicant: SHARP, KABUSHIKI KAISHAInventors: Ken-ichi Yanai, Yoshio Nagahiro, Kazushige Hotta, Koji Ohgata, Yasuyoshi Mishima, Nobuo Sasaki