Abstract: An error correction circuit (20) according to this invention includes a first error correction processing circuit (21) configured to perform error correction processing in a row direction on array data having undergone first coding in the row direction, an error detection processing circuit (26) configured to perform error detection processing in a column direction on the array data having undergone second coding in the column direction, a corrected-bit likelihood calculation circuit (24) configured to calculate for each row the sum of likelihoods of corrected bits each of which is a bit corrected by the first error correction processing circuit (21), a high-likelihood row detection circuit (25) configured to detect rows of the array data in the descending order of the sums of likelihoods of corrected bits of respective rows output from the corrected-bit likelihood calculation circuit (24), and a second error correction processing circuit (27) configured to correct a bit at which a column error-detected by th

Abstract: A frame synchronization system (1) according to this invention includes a frame signal generation circuit (20) configured to generate a frame signal including a plurality of first frame signals each including a first frame synchronization signal and a first payload signal, wherein the first frame synchronization signal is formed from at least one symbol and is set with an average amplitude lower than an average amplitude of the first payload signal, and a frame synchronization circuit (60) configured to receive the frame signal via an optical transmission path (70), and detect the first frame synchronization signal from a received signal, wherein the received signal is divided into frames having a symbol length of the first frame signal, coordinate values, on an IQ plane, of the signals at identical symbol positions of the plurality of divided frames are added over the plurality of frames, and a symbol specified by magnitude comparison in the frame based on an addition result is determined as the first frame

Abstract: An imaging device includes: a semiconductor substrate; a first photoelectric converter which is disposed in the semiconductor substrate; a second photoelectric converter different from the first photoelectric converter, which is disposed in the semiconductor substrate; a wiring layer disposed on or above the semiconductor substrate; and a capacitor which is disposed in the wiring layer and surrounds the first photoelectric converter in plan view. The capacitor includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first electrode is connected to one of the first photoelectric converter and the second photoelectric converter.

Abstract: An imaging device having a semiconductor substrate including: a semiconductor region including an impurity of a first conductivity type, a first diffusion region that is in contact with the semiconductor region, that includes an impurity of a second conductivity type different from the first conductivity type, and that converts incident light into charges, and a second diffusion region that includes an impurity of the second conductivity type and that directly accumulates at least a part of the charges generated in the first diffusion region. The imaging device further includes a contact plug in contact with the second diffusion region, and a capacitive element electrically connected to the second diffusion region through the contact plug.

Abstract: An imaging device includes a semiconductor substrate including a semiconductor region including an impurity of a first conductivity type, a first diffusion region that is in contact with the semiconductor region, that includes an impurity of a second conductivity type, and that converts incident light into charges, and a second diffusion region that includes an impurity of the second conductivity type and that accumulates at least a part of the charges flowing from the first diffusion region, a first transistor that includes a first gate electrode and that includes the second diffusion region as one of a source and a drain, a contact plug electrically connected to the second diffusion region, a capacitive element one end of which is electrically connected to the contact plug, and a second transistor that includes a second gate electrode, the second gate electrode being electrically connected to the one end of the capacitive element.

Abstract: An error correction device includes a first correction unit which performs error correction decoding of data by a repetitive operation, having a full operation state in which the error correction decoding is repeated until convergence is obtained and a save operation state in which the number of times of the repetitive operation is restricted to a predetermined number. An error information estimation unit estimates an input error rate or an output error rate of the first correction unit using a decoding result of the first correction unit, and a control unit which controls transition between the full operation state and the save operation state based on at least one piece of information of the input error rate, the output error rate, and an operation time of the first correction unit. It is thus possible to provide an error correction device that can improve a transmission characteristic while suppressing power consumption.

Abstract: A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination.

Abstract: Large diameter edges formed in arc shapes having curvature radii larger than a ball radius are provided. This allows improving surface roughness of a machined surface by cutting of a planar surface with the respective large diameter edges compared with cutting of a planar surface with a ball end cutting edge formed in an arc shape having a single curvature radius. Further, since the respective large diameter edges are formed in the arc shape, compared with cutting of a curved surface with linear cutting edges, surface roughness of a machined surface can be improved by cutting a curved surface with the respective large diameter edges. Accordingly, a pick feed during the cutting of the planar surface and the curved surface with the respective large diameter edges can be increased, and therefore machining efficiency in the cutting of both of the planar surface and the curved surface can be improved.

Abstract: A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination.

Abstract: A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination.

Abstract: A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination.

Abstract: An error correction device according to this invention includes a first correction unit configured to perform error correction decoding of data by a repetitive operation, and having a full operation state in which the repetitive operation of the error correction decoding is repeated until convergence is obtained and a save operation state in which the number of times of the repetitive operation of the error correction decoding is restricted to a predetermined number of times, an error information estimation unit configured to estimate an input error rate or an output error rate of the first correction unit using a decoding result of the first correction unit, and a control unit configured to control transition between the full operation state and the save operation state of the first correction unit based on at least one piece of information of the input error rate, the output error rate, and an operation time of the first correction unit.

Abstract: An imaging device includes: a semiconductor substrate; a first photoelectric converter which is disposed in the semiconductor substrate; a second photoelectric converter different from the first photoelectric converter, which is disposed in the semiconductor substrate; a wiring layer disposed on or above the semiconductor substrate; and a capacitor which is disposed in the wiring layer and surrounds the first photoelectric converter in plan view. The capacitor includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first electrode is connected to one of the first photoelectric converter and the second photoelectric converter.

Abstract: A solid-state imaging apparatus includes a plurality of high-sensitivity pixels that are arranged in a matrix, and perform a photoelectric conversion at a predetermined sensitivity; a plurality of low-sensitivity pixels that are arranged in a matrix in gaps between the plurality of high-sensitivity pixels, and perform a photoelectric conversion at a lower sensitivity than the predetermined sensitivity; and a signal processor that generates a pixel signal by (i) detecting a difference signal between a signal from the plurality of high-sensitivity pixels and a signal from the plurality of low-sensitivity pixels, and (ii) correcting the signal from the plurality of high-sensitivity pixels using the difference signal.

Abstract: An imaging device includes: a semiconductor substrate; a first photoelectric converter which is disposed in the semiconductor substrate; a second photoelectric converter different from the first photoelectric converter, which is disposed in the semiconductor substrate; a wiring layer disposed on or above the semiconductor substrate; and a capacitor which is disposed in the wiring layer and surrounds the first photoelectric converter in plan view. The capacitor includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first electrode is connected to one of the first photoelectric converter and the second photoelectric converter.

Abstract: An imaging device includes a semiconductor substrate including a semiconductor region including an impurity of a first conductivity type, a first diffusion region that is in contact with the semiconductor region, that includes an impurity of a second conductivity type, and that converts incident light into charges, and a second diffusion region that includes an impurity of the second conductivity type and that accumulates at least a part of the charges flowing from the first diffusion region, a first transistor that includes a first gate electrode and that includes the second diffusion region as one of a source and a drain, a contact plug electrically connected to the second diffusion region, a capacitive element one end of which is electrically connected to the contact plug, and a second transistor that includes a second gate electrode, the second gate electrode being electrically connected to the one end of the capacitive element.