Abstract: A packet receiving circuit splits the packet received from a transmission channel into a fixed length of cells and outputs the cells, a search key extracting circuit extracts a predetermined search key from the above-mentioned cells, a CAM performs retrieval based on the above-mentioned search key and outputs a memory address corresponding to the search key, a matching entry address receiving and associative data address transmitting circuit calculates the memory address of an associative data memory based on the above-mentioned memory address and outputs the information stored in the associative data memory as associative data, a search result (associative data) receiving circuit receives the above-mentioned associative data and performs header updating and destination address of the above-mentioned cells, and a packet transmitting circuit outputs the above-mentioned cells in the form of a packet to a transmission channel.

Abstract: A packet receiving circuit 11 splits the packet received from a transmission channel 1 into a fixed length of cells and outputs the cells, a search key extracting circuit 12 extracts a predetermined search key from the above-mentioned cells, a CAM 13 performs retrieval based on the above-mentioned search key and outputs a memory address corresponding to the search key, a matching entry address receiving and associative data address transmitting circuit 14 calculates the memory address of an associative data memory 15 based on the above-mentioned memory address and outputs the information stored in the associative data memory 15 as associative data, a search result (associative data) receiving circuit 16 receives the above-mentioned associative data and performs header updating and destination address of the above-mentioned cells, and a packet transmitting circuit 17 outputs the above-mentioned cells in the form of a packet to a transmission channel 2.

Abstract: An information retrieval system includes two content addressable memories to be searched for m-bit/n-bit codes identical with m-bit/n-bit retrieval key sub-codes, a data memory storing pieces of information relating to different retrieval keys expressed by the combinations of the m-bit/n-bit codes in addressable memory locations assigned addresses, respectively, and an address generating unit supplied with addresses of the m-bit/n-bit codes identical with the m-bit/n-bit retrieval key sub-codes from the content addressable memories so as to generate a target address from the addresses for accessing the piece of information relating to a given retrieval key, whereby the two content addressable memories are searched for the m-bit/n-bit codes substantially in parallel.