Patents by Inventor Yasuyuki Morishita
Yasuyuki Morishita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990465Abstract: A first ESD protection circuit is provided between a first high-potential side power supply and a first low-potential side power supply of a first power supply system and a second ESD protection circuit is provided between a second high-potential side power supply and a second low-potential side power supply of a second power supply system. A coupling circuit includes a bidirectional diode and couples the first and second low-potential side power supplies. A first transistor is composed of an n-channel MOS transistor, has a drain coupled to the first high-potential side power supply of the first power supply system, and has a back gate coupled to the second low-potential side power supply of the second power supply system. A resistor element is inserted in series between the drain of the first transistor and the first high-potential side power supply.Type: GrantFiled: June 16, 2021Date of Patent: May 21, 2024Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yasuyuki Morishita
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Patent number: 11901146Abstract: A relay drive control device is configured to control drive of a relay for connecting a battery mounted on a vehicle and an external power supply. The relay drive control device includes a controller configured to, when driving the relay, supply an output voltage of the battery to the relay after increasing the output voltage to a voltage value at which the relay is drivable.Type: GrantFiled: January 26, 2023Date of Patent: February 13, 2024Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Tomohiro Narematsu, Akira Umemoto, Takuya Itoh, Yasuyuki Morishita, Yu Shimizu, Fumiyoshi Kuribara, Ippei Takesue, Daiki Takayama, Tomoya Aoki, Daisuke Kamikihara
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Publication number: 20230298837Abstract: A relay drive control device is configured to control drive of a relay for connecting a battery mounted on a vehicle and an external power supply. The relay drive control device includes a controller configured to, when driving the relay, supply an output voltage of the battery to the relay after increasing the output voltage to a voltage value at which the relay is drivable.Type: ApplicationFiled: January 26, 2023Publication date: September 21, 2023Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Tomohiro NAREMATSU, Akira UMEMOTO, Takuya ITOH, Yasuyuki MORISHITA, Yu SHIMIZU, Fumiyoshi KURIBARA, Ippei TAKESUE, Daiki TAKAYAMA, Tomoya AOKI, Daisuke KAMIKIHARA
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Publication number: 20230139094Abstract: A semiconductor device includes an input/output cell, an IO power supply cell, a core power supply cell, and a core logic circuit arranged on a chip, and the core power supply cell includes an ESD protection circuit. The input/output cell includes a level shifter circuit and the level shifter circuit is arranged in the input/output cell. The core logic circuit is arranged outside the input/output cell. The core power supply cell is not arranged in the same row as the input/output cell, but is arranged in a third region provided between a first region in which the input/output cell and the IO power supply cell are arranged and a second region in which the core logic circuit is arranged.Type: ApplicationFiled: October 12, 2022Publication date: May 4, 2023Inventor: Yasuyuki MORISHITA
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Publication number: 20230092555Abstract: A semiconductor device includes a protection element configured by a MOSFET, and the protection element has a multilayer metal wiring structure. The multilayer metal wiring structure includes drain connection wirings connected to drain regions of the MOSFET and source connection wirings connected to source regions of the MOSFET. In a part of a layer of the multilayer metal wiring structure where both the drain connection wirings and the source connection wirings are present, only either the drain connection wirings or the source connection wirings are laid out in a grained pattern.Type: ApplicationFiled: September 15, 2022Publication date: March 23, 2023Applicant: Renesas Electronics Corporation.Inventor: Yasuyuki MORISHITA
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Patent number: 11512280Abstract: An object of the present invention is to provide a novel culturing method by which spores can be efficiently produced. The present invention further provides a method for culturing sporulating bacteria, comprising adding a sporulation-inhibiting substance into a medium for culturing sporulating bacteria, wherein the carbon content in the medium is 9.1 g/L or more, and preferably further comprising a step of adding a sporulation-accelerating substance to the medium.Type: GrantFiled: October 6, 2017Date of Patent: November 29, 2022Assignee: SDS BIOTECH K.K.Inventor: Yasuyuki Morishita
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Patent number: 11377632Abstract: The present invention provides a method for producing bacterial cells, which comprises, in a multi-stage liquid culture process for bacteria, culturing a bacterium in a liquid medium containing an antibiotic in a stage prior to the final stage, and then lowering the concentration of the antibiotic in the final stage to a level lower than that in the prior stage. Accordingly, bacterial cells can be produced with good productivity while suppressing the appearance of variants forming abnormal colonies among the bacteria obtained after culture.Type: GrantFiled: September 25, 2018Date of Patent: July 5, 2022Assignee: IDEMITSU KOSAN CO., LTD.Inventor: Yasuyuki Morishita
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Publication number: 20220020739Abstract: A first ESD protection circuit is provided between a first high-potential side power supply and a first low-potential side power supply of a first power supply system and a second ESD protection circuit is provided between a second high-potential side power supply and a second low-potential side power supply of a second power supply system. A coupling circuit includes a bidirectional diode and couples the first and second low-potential side power supplies. A first transistor is composed of an n-channel MOS transistor, has a drain coupled to the first high-potential side power supply of the first power supply system, and has a back gate coupled to the second low-potential side power supply of the second power supply system. A resistor element is inserted in series between the drain of the first transistor and the first high-potential side power supply.Type: ApplicationFiled: June 16, 2021Publication date: January 20, 2022Inventor: Yasuyuki MORISHITA
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Patent number: 11201465Abstract: A semiconductor device including a digital circuit, a first ground potential line provided corresponding to the digital circuit, an analog circuit, a second ground potential line respectively provided corresponding to the analog circuit, and a bidirectional diode group provided between the first ground potential line and the second ground potential line.Type: GrantFiled: July 26, 2019Date of Patent: December 14, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yasuyuki Morishita
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Patent number: 11008545Abstract: A method of producing Bacillus spores comprising a step of culturing the Bacillus bacterium using a liquid medium having a C/N ratio (weight ratio of carbon content to nitrogen content) of greater than 4 and less than 9.5.Type: GrantFiled: April 8, 2016Date of Patent: May 18, 2021Assignee: IDEMITSU KOSAN CO., LTD.Inventors: Takanori Eguchi, Yasuyuki Morishita, Yuki Tsukagoshi
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Patent number: 10790277Abstract: A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one side constituted by a chip edge in relation to the first input/output circuit, the second input/output circuit being connected to a second pad; and an ESD protective circuit disposed near the outer-side chip edge of the first and second input/output circuits. The ESD protection circuit is provided with a resistor, a capacitor, an inverter, and an N-channel-type transistor.Type: GrantFiled: June 19, 2015Date of Patent: September 29, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Satoshi Maeda, Yasuyuki Morishita, Masanori Tanaka
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Publication number: 20200277564Abstract: The present invention provides a method for producing bacterial cells, which comprises, in a multi-stage liquid culture process for bacteria, culturing a bacterium in a liquid medium containing an antibiotic in a stage prior to the final stage, and then lowering the concentration of the antibiotic in the final stage to a level lower than that in the prior stage. Accordingly, bacterial cells can be produced with good productivity while suppressing the appearance of variants forming abnormal colonies among the bacteria obtained after culture.Type: ApplicationFiled: September 25, 2018Publication date: September 3, 2020Applicant: IDEMITSU KOSAN CO.,LTD. IDEMITSU KOSAN CO.,LTD. IDEMITSU KOSAN CO.,LTD.Inventor: Yasuyuki MORISHITA
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Publication number: 20200040300Abstract: An object of the present invention is to provide a novel culturing method by which spores can be efficiently produced. The present invention further provides a method for culturing sporulating bacteria, comprising adding a sporulation-inhibiting substance into a medium for culturing sporulating bacteria, wherein the carbon content in the medium is 9.1 g/L or more, and preferably further comprising a step of adding a sporulation-accelerating substance to the medium.Type: ApplicationFiled: October 6, 2017Publication date: February 6, 2020Applicant: IDEMITSU KOSAN CO., LTD.Inventor: Yasuyuki MORISHITA
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Publication number: 20190348835Abstract: A semiconductor device including a digital circuit, a first ground potential line provided corresponding to the digital circuit, an analog circuit, a second ground potential line respectively provided corresponding to the analog circuit, and a bidirectional diode group provided between the first ground potential line and the second ground potential line.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Inventor: Yasuyuki MORISHITA
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Patent number: 10424920Abstract: A semiconductor device that can have both noise resistance and ESD resistance is provided. The semiconductor device includes a first and a second digital circuits, a first and a second ground potential lines respectively provided corresponding to the first and the second digital circuits, a first and a second analog circuits, a third and a fourth ground potential lines respectively provided corresponding to the first and the second analog circuits, a first bidirectional diode group provided between the first and the second ground potential lines, a second bidirectional diode group provided between the third and the fourth ground potential lines, and a third bidirectional diode group provided between the first and the third ground potential lines. The number of stages of bidirectional diodes of the third bidirectional diode group is greater than that included in each of the first and the second bidirectional diode groups.Type: GrantFiled: March 24, 2017Date of Patent: September 24, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yasuyuki Morishita
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Patent number: 10256228Abstract: A semiconductor device includes a MOS transistor which is coupled between two terminals and discharges current which flows caused by generation of static electricity and a diode which is coupled between a back gate of the MOS transistor and one of the terminal and has a polarity which is reversed to the polarity of a parasitic diode which is formed between the back gate and a source of the MOS transistor.Type: GrantFiled: December 29, 2017Date of Patent: April 9, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshihito Uzawa, Yasuyuki Morishita, Masanori Tanaka
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Publication number: 20190048311Abstract: A method of producing Bacillus spores comprising a step of culturing the Bacillus bacterium using a liquid medium having a C/N ratio (weight ratio of carbon content to nitrogen content) of greater than 4 and less than 9.5.Type: ApplicationFiled: April 8, 2016Publication date: February 14, 2019Applicant: IDEMITSU KOSAN CO., LTD.Inventors: Takanori EGUCHI, Yasuyuki MORISHITA, Yuki TSUKAGOSHI
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Patent number: 10111423Abstract: The present invention relates to a microbial pesticide composition, which is obtained by a method including the steps of: adjusting a pH of a culture solution of the Bacillus sp. bacterium to from 3.0 to 5.0 (pH adjustment step); mixing the culture solution with the calcium chloride and/or the magnesium sulfate (mixing step); and lyophilizing or spray-drying the culture solution (drying step). In the microbial pesticide composition, even if it is stored for a long period of time at room temperature, the active ingredient remains stable and a sufficient preventive effect against plant disease can be maintained.Type: GrantFiled: April 7, 2015Date of Patent: October 30, 2018Assignees: SDS BIOTECH K.K., Idemitsu Kosan Co., Ltd.Inventors: Mutsumi Miyazaki, Yusuke Amaki, Keijitsu Tanaka, Yasuyuki Morishita, Takanori Eguchi
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Publication number: 20180211949Abstract: A semiconductor device includes a MOS transistor which is coupled between two terminals and discharges current which flows caused by generation of static electricity and a diode which is coupled between a back gate of the MOS transistor and one of the terminal and has a polarity which is reversed to the polarity of a parasitic diode which is formed between the back gate and a source of the MOS transistor.Type: ApplicationFiled: December 29, 2017Publication date: July 26, 2018Inventors: Yoshihito UZAWA, Yasuyuki MORISHITA, Masanori TANAKA
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Publication number: 20180040609Abstract: A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one side constituted by a chip edge in relation to the first input/output circuit, the second input/output circuit being connected to a second pad; and an ESD protective circuit disposed near the outer-side chip edge of the first and second input/output circuits. The ESD protection circuit is provided with a resistor, a capacitor, an inverter, and an N-channel-type transistor.Type: ApplicationFiled: June 19, 2015Publication date: February 8, 2018Applicant: Renesas Electronics CorporationInventors: Satoshi MAEDA, Yasuyuki MORISHITA, Masanori TANAKA