Abstract: A detection device has a pinching sensor and a detecting unit. The pinching sensor has a dielectric layer in which a linear conductor layer is formed, and conductor layers arranged on top and bottom surfaces of the dielectric layer, a slit being formed on at least one of the conductor layers arranged on the top and bottom surfaces. The detecting unit supplies a high-frequency signal to an input portion of the linear conductor layer, generates an electric field around a slit portion of the conductor layer on which the slit is formed, and detects a change in a reflection coefficient at the input portion, the change being caused by a change of the electric field generated by interference with a detected object.

Abstract: According to one embodiment, a sensor system includes a sensor node that collects data; and a data collection apparatus that is wirelessly connected to the sensor node. The sensor node encrypts the sensor data measured by the sensor device using the received encryption key according to the received measurement parameter and transmits the encrypted sensor data to the data collection apparatus. The data collection apparatus decrypts the sensor data received from the sensor node, stores the decrypted sensor data in a storage unit when the sensor data is normally decrypted, and discards non-decrypted sensor data and transmits the measurement parameter and the encryption key to the sensor node when the sensor data is not normally decrypted.

Abstract: An ultrasound diagnosis device includes: an ultrasound probe which transmits an ultrasound wave toward a examinee and receives a reflected wave from the examinee; and a main device which controls the transmitting and receiving of the ultrasound waves from the ultrasound probe and is operated to receive a receiving signal obtained by receiving the reflected wave from the examinee by the ultrasound probe, to generate an ultrasound image of the examinee, and to display the ultrasound image on a display screen, wherein the ultrasound probe includes a plurality of subarrays having a plurality of element circuits transmitting and receiving ultrasound signals and a plurality of reference voltage sources, and the plurality of subarrays and the plurality of reference voltage sources have a one-to-one correspondence.

Abstract: According to one embodiment, a sensor system includes a sensor node that collects data; and a data collection apparatus that is wirelessly connected to the sensor node. The sensor node encrypts the sensor data measured by the sensor device using the received encryption key according to the received measurement parameter and transmits the encrypted sensor data to the data collection apparatus. The data collection apparatus decrypts the sensor data received from the sensor node, stores the decrypted sensor data in a storage unit when the sensor data is normally decrypted, and discards non-decrypted sensor data and transmits the measurement parameter and the encryption key to the sensor node when the sensor data is not normally decrypted.

Abstract: A detection device has a pinching sensor and a detecting unit. The pinching sensor has a dielectric layer in which a linear conductor layer is formed, and conductor layers arranged on top and bottom surfaces of the dielectric layer, a slit being formed on at least one of the conductor layers arranged on the top and bottom surfaces. The detecting unit supplies a high-frequency signal to an input portion of the linear conductor layer, generates an electric field around a slit portion of the conductor layer on which the slit is formed, and detects a change in a reflection coefficient at the input portion, the change being caused by a change of the electric field generated by interference with a detected object.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: An ultrasound diagnosis device includes: an ultrasound probe which transmits an ultrasound wave toward a examinee and receives a reflected wave from the examinee; and a main device which controls the transmitting and receiving of the ultrasound waves from the ultrasound probe and is operated to receive a receiving signal obtained by receiving the reflected wave from the examinee by the ultrasound probe, to generate an ultrasound image of the examinee, and to display the ultrasound image on a display screen, wherein the ultrasound probe includes a plurality of subarrays having a plurality of element circuits transmitting and receiving ultrasound signals and a plurality of reference voltage sources, and the plurality of subarrays and the plurality of reference voltage sources have a one-to-one correspondence.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: A power supply circuit has: an input terminal; an output terminal; and a digital power supply circuit and an analog power supply circuit connected in parallel between the input terminal and the output terminal. Further desirably, the analog power supply circuit is a circuit that the minimum resistance value of an output equivalent resistance between an input terminal and an output terminal of the analog power supply circuit is an output equivalent resistance equal to or lower than the minimum ON resistance among those of switch circuits configuring the switch array unit of the digital power supply circuit and having a plurality of ON resistances, or a circuit that the minimum resistance value is an output equivalent resistance equal to or lower than the minimum resistance value among those of switch circuits configuring the switch array unit of the digital power supply circuit and having series-connected resistances having resistance values.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: A power supply circuit has: an input terminal; an output terminal; and a digital power supply circuit and an analog power supply circuit connected in parallel between the input terminal and the output terminal. Further desirably, the analog power supply circuit is a circuit that the minimum resistance value of an output equivalent resistance between an input terminal and an output terminal of the analog power supply circuit is an output equivalent resistance equal to or lower than the minimum ON resistance among those of switch circuits configuring the switch array unit of the digital power supply circuit and having a plurality of ON resistances, or a circuit that the minimum resistance value is an output equivalent resistance equal to or lower than the minimum resistance value among those of switch circuits configuring the switch array unit of the digital power supply circuit and having series-connected resistances having resistance values.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: To provide a voltage regulator capable of stably obtaining a desired output voltage even in a low-voltage operation with a voltage equal to or lower than 1 V, the voltage regulator includes a switch array in which a plurality of switches are connected in parallel, a switch state register storing an ON or OFF state of each of the switches in the switch array, and a comparator comparing a reference voltage and a voltage of an output terminal coupled to an output of the switch array and outputting a comparison result as a digital value, and a state of each of the switches in the switch array is changed by updating a value of the switch state register in accordance with the output of the digital value from the comparator.