Patents by Inventor Yasuyuki Sakashita

Yasuyuki Sakashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060197229
    Abstract: According to the present invention, one or more reinforcing vias (7) or reinforcing metal layers are disposed on the inner side of connecting electrodes (5). With this configuration, strength increases relative to a load applied for mounting a semiconductor element (3) and the sinking of the connecting electrodes (5) is reduced. Thus, it is possible to reduce the connecting stress of the semiconductor device, reduce the deformation of a joint, and increase flexibility in process design.
    Type: Application
    Filed: February 28, 2006
    Publication date: September 7, 2006
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takatoshi Osumi, Yasuyuki Sakashita
  • Patent number: 5622590
    Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in an array. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: April 22, 1997
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
  • Patent number: 5550408
    Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in a matrix. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: August 27, 1996
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama
  • Patent number: 5436503
    Abstract: The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in an array. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.
    Type: Grant
    Filed: November 17, 1993
    Date of Patent: July 25, 1995
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshinobu Kunitomo, Makoto Nozu, Yasuyuki Sakashita, Masahide Tsukamoto, Seiichi Nakatani, Keiji Saeki, Yoshifumi Kitayama