Abstract: A controlling device includes a controller that executes control to functionally activate of, at least, a part of transmission lanes in multiple transmission lanes connecting a plurality of subsystems which run based on a lock-step method and an embedder that executes an embedding operation to realize a multiplexing state using the part of transmission lanes controlled to functionally activate by the controller and the plurality of the subsystems, wherein, the controller determines whether or not the embedding operation succeeds, determines, when the embedding operation fails, whether or not an embedding operation using another part of transmission lanes, of the multiple transmission lanes, different from the part of transmission lanes used in the failure embedding operation, and executes, when the corporation processing succeeds, control to functionally activate the another part of transmission lanes.

Abstract: A controlling device 501 includes a controller 502 that executes control to functionally activate of, at least, a part of transmission lanes in multiple transmission lanes connecting a plurality of subsystems which run based on a lock-step method and an embedder 503 that executes an embedding operation to realize a multiplexing state using the part of transmission lanes controlled to functionally activate by the controller and the plurality of the subsystems, wherein, the controller determines whether or not the embedding operation succeeds, determines, when the embedding operation fails, whether or not an embedding operation using another part of transmission lanes, of the multiple transmission lanes, different from the part of transmission lanes used in the failure embedding operation, and executes, when the corporation processing succeeds, control to functionally activate the another part of transmission lanes.

Abstract: A control device according to an exemplary aspect of the present invention, which is included in a sub-system of a plurality of sub-systems included in a fault tolerant system, includes: a packet reception unit that receives data from a processor unit included in the plurality of sub systems each including: the processor unit; an input-output unit; and a signal transmission path, the control device being connected between the processor unit and the input-output unit; and a first transmission unit that transmits error detection data being generated from the data of accessing from the processor unit to the input-output unit in an own sub-system to an companion sub-system when the processor unit is in the lockstep synchronous state, and transmits the data of accessing from a processor unit to the input-output unit in the own sub-system to the companion sub-system when the processor is in a lockstep asynchronous state.

Abstract: A control device according to an exemplary aspect of the present invention, which is included in a sub-system of a plurality of sub-systems included in a fault tolerant system, includes: a packet reception unit that receives data from a processor unit included in the plurality of sub systems each including: the processor unit; an input-output unit; and a signal transmission path, the control device being connected between the processor unit and the input-output unit; and a first transmission unit that transmits error detection data being generated from the data of accessing from the processor unit to the input-output unit in an own sub-system to an companion sub-system when the processor unit is in the lockstep synchronous state, and transmits the data of accessing from a processor unit to the input-output unit in the own sub-system to the companion sub-system when the processor is in a lockstep asynchronous state.

Abstract: A multiplex apparatus includes a plurality of systems configured to be connected to each other by links. Each of the plurality of systems includes a CPU, a pseudo legacy device and a legacy device. The pseudo legacy device is configured to be electrically connected to the CPU. The legacy device is configured to be electrically connected to the pseudo legacy device. The pseudo legacy device includes a request buffer and a pseudo operator. The request buffer is configured to store a request when the CPU sends the request through the pseudo legacy device to the legacy device. The pseudo operator is configured to execute an emulation with regard to the legacy device based on the request, and store the emulation result including an inside status of the legacy device.

Abstract: A data processing apparatus includes a plurality of CPU modules each including a CPU. Each of the plurality of CPU module includes a clock source, a clock counter, an I/O module, a first data adder, and a timing adjuster. The first data adder reads a value of the clock counter, adds a predetermined offset value to the read value to generate a timing value, and adds the generated timing value to the packet designated to the CPU. The timing adjuster adjusts timing of transmitting the packet to the CPU, based on the timing value of the packet received from the first data adder and the value of the clock counter.

Abstract: A multiplex apparatus includes a plurality of systems configured to be connected to each other by links. Each of the plurality of systems includes a CPU, a pseudo legacy device and a legacy device. The pseudo legacy device is configured to be electrically connected to the CPU. The legacy device is configured to be electrically connected to the pseudo legacy device. The pseudo legacy device includes a request buffer and a pseudo operator. The request buffer is configured to store a request when the CPU sends the request through the pseudo legacy device to the legacy device. The pseudo operator is configured to execute an emulation with regard to the legacy device based on the request, and store the emulation result including an inside status of the legacy device.

Abstract: An information processing apparatus is disclosed which can discriminate, even when the orders of output data of a plurality of CPU modules differ from each other, whether or not the operations of the CPU modules coincide with each other. The information processing apparatus includes two first and second CPU modules which perform the same process in synchronism with each other and an I/O module connected to the CPU modules. The I/O module receives output data of the two CPU modules and compares a plurality of output data of the first CPU module and a plurality of output data of the second CPU module with each other with the output data adjusted in order so as to correspond to each other to discriminate whether or not the output data coincide with each other.