Abstract: A speed converting apparatus with a load controlling function comprises a first interface unit operating for an emulation device according to a system clock of the emulation device, a second interface unit operating for an arithmetic unit according to a system clock of the arithmetic unit, and a load controlling unit controlling at least either a load of a request outputted to the emulation device on the emulation device or a load of a request outputted to the arithmetic unit on the arithmetic unit. In performance verification or connection verification of a target to be verified, the speed converting apparatus can vary a load of a request issued to the target to be verified on the target or a load issued to a verification device on the verification device, while absorbing a difference in operation speed between the target to be verified and the verification device.

Abstract: A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.

Abstract: An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.

Abstract: A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.

Abstract: There is provided a gateway apparatus that controls a forwarding process of frame data between multiple communication channels, said gateway apparatus including a search engine that is respectively provided for each of the multiple communication channels to route the frame data between the multiple communication channels, and a first storage portion that is respectively provided for each of the multiple communication channels to temporarily stores the frame data routed.

Abstract: A data transfer device for storing only transfer data for which updating is necessary in the storage unit of a transfer source, transferring the transfer data by a transfer control unit, temporarily storing the transfer data in a register provided in a transfer destination circuit, transferring the transfer data stored in the register to the discontinuous storage area of the transfer destination circuit according to the map information of a map register, and transferring data for which updating is necessary to the transfer destination circuit.

Abstract: An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.

Abstract: A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.

Abstract: A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.

Abstract: There is provided a gateway apparatus that controls a forwarding process of frame data between multiple communication channels, said gateway apparatus including a search engine that is respectively provided for each of the multiple communication channels to route the frame data between the multiple communication channels, and a first storage portion that is respectively provided for each of the multiple communication channels to temporarily stores the frame data routed.

Abstract: A speed converting apparatus with a load controlling function comprises a first interface unit operating for an emulation device according to a system clock of the emulation device, a second interface unit operating for an arithmetic unit according to a system clock of the arithmetic unit, and a load controlling unit controlling at least either a load of a request outputted to the emulation device on the emulation device or a load of a request outputted to the arithmetic unit on the arithmetic unit. In performance verification or connection verification of a target to be verified, the speed converting apparatus can vary a load of a request issued to the target to be verified on the target or a load issued to a verification device on the verification device, while absorbing a difference in operation speed between the target to be verified and the verification device.

Abstract: A packet processing device which can reserve a calculation time for each instruction procedure execution unit independent of the data length of a packet by sequentially selecting an instruction procedure execution unit by a selection signal generation unit and performing a calculation on each packet when packets are consecutively input to a packet access unit is disclosed.

Abstract: A packet processor having a general-purpose arithmetic operator and another dedicated circuit, which extracts a particular field from the general-purpose register as object field, on which the predetermined general-purpose arithmetic operation is to be performed by the general-purpose arithmetic operator and writes a result of the arithmetic operation by the general-purpose arithmetic operator into the general-purpose register as updated information of the particular field. Based on the extraction and write process of the packet field designated by software (instructions), the packet processor realizes high flexibility and high speed processing.

Abstract: A packet-data-processing apparatus includes a first data-processing unit for computing information on a processing count; a memory; a second data-processing-unit for processing the input packet and storing first results in the memory; an access mechanism unit for reading out one of the first results written into the memory least recently from the memory at a request for a read operation and deleting the result of processing read out from the memory; a third data-processing unit for making the request for a read operation and carrying out processing based on the first result read out by the access control unit at the request and an input packet associated with the result of processing; and fourth data-processing unit constituting pipeline data-processing mechanism with the first and third data-processing unit.

Abstract: A packet-data-processing apparatus includes a first data-processing unit for computing information on a processing count; a memory; a second data-processing-unit for processing the input packet and storing first results in the memory; an access mechanism unit for reading out one of the first results written into the memory least recently from the memory at a request for a read operation and deleting the result of processing read out from the memory; a third data-processing unit for making the request for a read operation and carrying out processing based on the first result read out by the access control unit at the request and an input packet associated with the result of processing; and fourth data-processing unit constituting pipeline data-processing mechanism with said first and third data-processing unit.

Abstract: The packet processing device which can reserve a calculation time for each instruction procedure execution unit independent of the data length of a packet by sequentially selecting an instruction procedure execution unit by a selection signal generation unit and performing a calculation on each packet when packets are consecutively input to a packet access unit is disclosed.

Abstract: A packet processor having a general-purpose arithmetic operator and another dedicated circuit, which extracts a particular field from the general-purpose register as object field, on which the predetermined general-purpose arithmetic operation is to be performed by the general-purpose arithmetic operator and writes a result of the arithmetic operation by the general-purpose arithmetic operator into the general-purpose register as updated information of the particular field. Based on the extraction and write process of the packet field designated by software (instructions), the packet processor realizes high flexibility and high speed processing.