Patents by Inventor Yat To William Wong
Yat To William Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8643337Abstract: A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.Type: GrantFiled: July 8, 2011Date of Patent: February 4, 2014Assignee: Hong Kong Applied Science & Technology Research Institute Company Ltd.Inventors: Kwok Kuen David Kwong, Yat To William Wong, Ho Ming Karen Wan, Chik Wai David Ng
-
Patent number: 8471744Abstract: An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.Type: GrantFiled: December 1, 2011Date of Patent: June 25, 2013Assignee: Hong Kong Applied Science & Technology Research Institute Company, Ltd.Inventors: Ho Ming (Karen) Wan, Yat To (William) Wong, Kwai Chi Chan
-
Publication number: 20130141264Abstract: An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.Type: ApplicationFiled: December 1, 2011Publication date: June 6, 2013Applicant: Hong Kong Applied Science & Technology Research Institute Company LimitedInventors: Ho Ming (Karen) WAN, Yat To (William) WONG, Kwai Chi CHAN
-
Patent number: 8421658Abstract: A Successive-Approximation Register Analog-to-Digital Converter (SAR-ADC) predicts compensation values for use in a future cycle. A compensation value is applied to capacitors in a calibration Y-side capacitor array to compensate for capacitance errors in a binary-weighted X-side capacitor array. Two compute engines pre-calculate predicted-0 and predicted-1 compensation values for a next bit to be converted. At the end of the current cycle when the comparator determines the current bit, the comparator also controls a mux to select one of the two predicted compensation values. Thus the compensation value is available at the beginning of the next bit's cycle, eliminating a long calculation delay. The compensation value for the first bit to be converted, such as the MSB, is calculated during calibration. Compensation values for other bits are data-dependent. Calibration values are accumulated during calibration to generate the first conversion compensation value for the first bit to be converted.Type: GrantFiled: November 24, 2011Date of Patent: April 16, 2013Assignee: Hong Kong Applied Science & Technology Research Institute Company, Ltd.Inventors: Hok Mo Yau, Tin Ho (Andy) Wu, Kam Chuen Wan, Yat To (William) Wong
-
Patent number: 8421660Abstract: A cascaded sigma-delta modulator has several modulator loops that have one or two sets of integrators, summers, and scalers, and a quantizer that generates a loop output. Input muxes to each loop select either an overall input or the loop output from a prior loop, allowing the modulator loops to be cascaded in series or to operate separately. Filter-configuring muxes after each modulator loop select either that loop's output or a loop output from any prior loop, or a zero. Each filter-configuring mux drives an input to a modified CIC filter. The modified CIC filter has an initial delay stage that receives the first filter-configuring mux output, and successive integrator stages that each receives a successive filter-configuring mux output. The modified CIC filter is a combination of a digital transform filter and a Cascaded-Integrator-Comb (CIC) filter. Modulator loops are powered down for lower-performance configurations or cascaded together for higher-performance configurations.Type: GrantFiled: November 25, 2011Date of Patent: April 16, 2013Assignee: Hong Kong Applied Science & Technology Research Institute Company., Ltd.Inventors: Ho Ming (Karen) Wan, Yat To (William) Wong, Kwai Chi Chan, Andrea Baschirotto
-
Patent number: 8416107Abstract: A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.Type: GrantFiled: September 28, 2011Date of Patent: April 9, 2013Assignee: Hong Kong Applied Science & Technology Research Institute Company Ltd.Inventors: Kam Chuen Wan, Yat To (William) Wong, Ho Ming (Karen) Wan, Kwai Chi Chan
-
Publication number: 20130076546Abstract: A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.Type: ApplicationFiled: September 28, 2011Publication date: March 28, 2013Applicant: Hong Kong Applied Science & Technology Research Institute Company LimitedInventors: Kam Chuen WAN, Yat To (William) WONG, Ho Ming (Karen) WAN, Kwai Chi CHAN
-
Patent number: 8258864Abstract: A pre-amplifier circuit can be cascaded and drive a latch for use in a precision analog-to-digital converter (ADC). The pre-amplifier has a main section and a feedback section connected by feedback resistors that do not produce voltage drops in the main section. Offset is stored on offset capacitors during an autozeroing phase and isolated by transmission gates during an amplifying phase. The offset capacitors drive the gates of feedback transistors that drive output nodes in the main section. Autozeroing sink transistors in the feedback section operate in the linear region while current sink transistors in the main section operate in the saturated region. Kickback-charge isolation transistors may be added for charge isolation. The output may also be equalized by an equalizing transmission gate. A very low power-supply voltage is supported even for high-speed operation with offset cancellation, due to the folded feedback resistor arrangement.Type: GrantFiled: September 21, 2011Date of Patent: September 4, 2012Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.Inventors: Kwai Chi Chan, Yat To (William) Wong, Ho Ming (Karen) Wan, Kam Chuen Wan, Kwok Kuen (David) Kwong
-
Patent number: 8193854Abstract: A bandgap reference circuit has trimming-up resistors and trimming-down resistors for bi-directional trimming. PNP transistors have base and collectors grounded and emitters connected to parallel resistors. A difference resistor drives an inverting input of an op amp that drives a transistor that generates the bandgap reference voltage Vbg. A sensing resistor connects Vbg to a splitting node that connects to the non-inverting input through a first parallel resistor. The splitting node also connects through a second parallel resistor to the inverting input. Fuses or switches enable the trimming-up and trimming-down resistors. The trimming-up resistors are in series with the sensing resistor and the trimming-down resistors are in series with an output resistor that connects Vbg to reference voltage Vref. The circuit can be designed for a more typical process since bi-directional trimming allows Vref to be raised or lowered. Many circuits need no trimming when targeted for the typical process.Type: GrantFiled: January 4, 2010Date of Patent: June 5, 2012Assignee: Hong Kong Applied Science and Technology Research Institute Company, Ltd.Inventors: Xiao Fei Kuang, Kam Chuen Wan, Kwai Chi Chan, Yat To (William) Wong, Kwok Kuen (David) Kwong
-
Patent number: 7999512Abstract: A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.Type: GrantFiled: December 16, 2008Date of Patent: August 16, 2011Assignee: Hong Kong Applied Science & Technology Research Institute Company, Ltd.Inventors: Kwok Kuen David Kwong, Yat To William Wong, Ho Ming Karen Wan, Chik Wai David Ng
-
Publication number: 20110163799Abstract: A bandgap reference circuit has trimming-up resistors and trimming-down resistors for bi-directional trimming. PNP transistors have base and collectors grounded and emitters connected to parallel resistors. A difference resistor drives an inverting input of an op amp that drives a transistor that generates the bandgap reference voltage Vbg. A sensing resistor connects Vbg to a splitting node that connects to the non-inverting input through a first parallel resistor. The splitting node also connects through a second parallel resistor to the inverting input. Fuses or switches enable the trimming-up and trimming-down resistors. The trimming-up resistors are in series with the sensing resistor and the trimming-down resistors are in series with an output resistor that connects Vbg to reference voltage Vref. The circuit can be designed for a more typical process since bi-directional trimming allows Vref to be raised or lowered. Many circuits need no trimming when targeted for the typical process.Type: ApplicationFiled: January 4, 2010Publication date: July 7, 2011Applicant: Hong Kong Applied Science & Technology Research Institute Company LimitedInventors: Xiao Fei KUANG, Kam Chuen WAN, Kwai Chi CHAN, Yat To (William) WONG, Kwok Kuen (David) KWONG
-
Patent number: 7812757Abstract: A hybrid Analog-to-Digital Converter (ADC) has a binary-weighted capacitor array and a sub-voltage capacitor array that are coupled together by a coupling capacitor. The sub-voltage capacitor array uses a minimum capacitor size that matches the minimum capacitor size of the binary-weighted capacitor array. The coupling capacitor is double the minimum size and reduces a voltage effect on a charge sharing line by half. Second coupling capacitors in the sub-voltage capacitor array each reduce the voltage effect by half, so that first, second, and third sub-voltage capacitors in the sub-voltage capacitor array produce ½, ¼, and ? voltage swings using the minimum size capacitance. Only MSB capacitors in the binary-weighted capacitor array sample the analog input voltage. During conversion, MSB's from a Successive-Approximation-Register (SAR) are applied to binary-weighted capacitors while LSB's are applied to sub-voltage capacitors.Type: GrantFiled: June 12, 2009Date of Patent: October 12, 2010Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.Inventors: Yat To William Wong, Kam Chuen Wan, Kwok Kuen David Kwong
-
Patent number: 7795976Abstract: An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers.Type: GrantFiled: December 30, 2008Date of Patent: September 14, 2010Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.Inventors: Yat To William Wong, Chik Wai David Ng, Ho Ming Karen Wan, Kam Chuen Wan, Kwok Kuen David Kwong
-
Patent number: 7764215Abstract: An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.Type: GrantFiled: December 31, 2008Date of Patent: July 27, 2010Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.Inventors: Ho Ming Karen Wan, Yat To William Wong, Kwai Chi Chan, Kwok Kuen David Kwong
-
Publication number: 20100164625Abstract: An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Applicant: Hong Kong Applied Science & Technology Research Institute Company LimitedInventors: Yat To (William) Wong, Chik Wai (David) Ng, Ho Ming (Karen) Wan, Kam Chuen Wan, Kwok Kuen (David) Kwong
-
Publication number: 20100164770Abstract: An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Applicant: Hong Kong Applied Science & Technology Research Institute Company LimitedInventors: Ho Ming (Karen) Wan, Yat To (William) Wong, Kwai Chi Chan, Kwok Kuen Kwong
-
Publication number: 20100164761Abstract: A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Applicant: Hong Kong Applied Science & Technology Research Institute Company LimitedInventors: Ho Ming Karen Wan, Yat To William Wong, Kwai Chi Chan, Hok Mo Yau, Tin Ho Andy Wu, Kwok Kuen David Kwong
-
Patent number: 7741981Abstract: A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.Type: GrantFiled: December 30, 2008Date of Patent: June 22, 2010Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.Inventors: Ho Ming Karen Wan, Yat To William Wong, Kwai Chi Chan, Hok Mo Yau, Tin Ho Andy Wu, Kwok Kuen David Kwong
-
Patent number: 7710094Abstract: A power converter has a power transistor driving a power current through an inductor to provide a controlled power-supply voltage. The power transistor is on during a first state but off during a second state when a sink transistor reduces the power current through the inductor. Both voltage sensing of the power-supply voltage and current sensing at the power transistor provide feedback to control the amount of time that the first state is active, and thus control the power current. Current sensing is provided by a smaller minor transistor in parallel with the power transistor. The minor transistor turns on after the power transistor to reduce disturbance spikes. Switches connect sources of the power and mirror transistors to an amplifier that drives a sensing transistor. The sensing transistor generates a sensing voltage from the mirror transistor source. During the second state the amplifier's inputs are equalized to provide fast response.Type: GrantFiled: December 12, 2008Date of Patent: May 4, 2010Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.Inventors: Yat To William Wong, Xiao Fei Kuang, Kam Chuen Wan, Kwok Kuen David Kwong
-
Patent number: 7705685Abstract: An oscillator operates at a very low voltage yet has a duty cycle that is set by a ratio of capacitors that are charged and discharged. Sub-threshold p-channel transistors conduct sub-threshold currents below the normal threshold voltage, and drive set and reset inputs of a set-reset S-R latch. The S-R latch drives the oscillator outputs. The oscillator outputs feed back to charging p-channel transistors that charge one plate of the capacitors. During half of the cycle, the charging p-channel transistor is off, allowing one plate of the capacitors to discharge through an n-channel discharge transistor. After a period of discharge determined by the capacitance of the capacitor, the gate of a sub-threshold p-channel transistor falls enough for sub-threshold current to flow, triggering the set or reset input of the S-R latch. Since sub-threshold currents are needed to toggle the S-R latch, the oscillator begins to oscillate below the threshold voltage.Type: GrantFiled: December 6, 2007Date of Patent: April 27, 2010Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.Inventors: Chik Wai David Ng, Yat To William Wong, Ho Ming Karen Wan, Kwok Kuen David Kwong