Patents by Inventor Yau-Ren Jenq

Yau-Ren Jenq has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090116184
    Abstract: An exclusive protection device for a PCMCIA card/express card, includes a shell, a liquid crystal display and a control unit. The inner surface of the shell defines a slot and the outer surface defines a chamber. The slot is disposed to receive a PCMCIA card or an express card. The liquid crystal display is fixed in the chamber of the shell. The control unit is disposed in the shell and connected to the liquid crystal display. Accordingly, not only can this protection device provides protection for the PCMCIA card/express card, but it also possesses many additional functions, such as a display function, a broadcast function, a transfer function and a telephone communication function.
    Type: Application
    Filed: October 1, 2008
    Publication date: May 7, 2009
    Inventor: Yau-Ren Jenq
  • Patent number: 7039005
    Abstract: A system and method of protection switching in a communications network that makes more efficient use of resources in the network and reduces the loss of data traffic carried by the network. The communications network includes an established working path and an established protect path interconnecting a source node and a sink node. The source node and the sink node are configured to perform label switching on the network. The source node receives primary data traffic and secondary data traffic over one or more communications paths. In a fault-free condition, the source node sends the primary data traffic over the working path to the sink node, and sends the secondary data traffic over the protect path to the sink node. In the event of a fault or switchover condition in the working path, the source node performs traffic trunk and label merging on the primary and secondary traffic, and sends the merged traffic over the protect path to the sink node.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: May 2, 2006
    Assignee: Fujitsu Limited
    Inventors: Yau-Ren Jenq, Indra Widjaja
  • Publication number: 20030063560
    Abstract: A system and method of protection switching in a communications network that makes more efficient use of resources in the network and reduces the loss of data traffic carried by the network. The communications network includes an established working path and an established protect path interconnecting a source node and a sink node. The source node and the sink node are configured to perform label switching on the network. The source node receives primary data traffic and secondary data traffic over one or more communications paths. In a fault-free condition, the source node sends the primary data traffic over the working path to the sink node, and sends the secondary data traffic over the protect path to the sink node. In the event of a fault or switchover condition in the working path, the source node performs traffic trunk and label merging on the primary and secondary traffic, and sends the merged traffic over the protect path to the sink node.
    Type: Application
    Filed: October 2, 2001
    Publication date: April 3, 2003
    Applicant: FUJITSU NETWORK COMMUNICATIONS, INC.
    Inventors: Yau-Ren Jenq, Indra Widjaja
  • Patent number: 6389031
    Abstract: A hierarchical searching technique is used to find the first memory location of a calendar queue with a validity bit of “1” (that is, the lowest time stamp). The bit string at any level l (l≠0) can be stored in a RAM of size glMl−1. The string at the highest level in the hierarchy (l=0) can be stored in an M0 bit register.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: May 14, 2002
    Assignee: Polytechnic University
    Inventors: Hung-Hsiang Jonathan Chao, Yau-Ren Jenq
  • Patent number: 6370144
    Abstract: A two (2) dimensional shaper uses a hierarchical searching technique to find the first memory location of the calendar queue with a validity bit of “1” (that is, the lowest time stamp). The bit string at any level l (l≠0) can be stored in a RAM of size glMl−1. The string at the highest level in the hierarchy (l=0) can be stored in an M0 bit register.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: April 9, 2002
    Assignee: Polytechnic University
    Inventors: Hung-Hsiang Jonathan Chao, Yau-Ren Jenq