Abstract: An authentication article includes: a substrate including: a first surface; a second surface disposed laterally to the first surface and at a depth below the first surface; and a plurality of indentations including the depth at the second surface of the substrate; and an array disposed on the substrate and including a plurality of analytes, the analytes being disposed in the indentations at a depth below a first surface of the substrate and provided to emit an authentication signature in response to being subjected to a probe stimulus. A process for authenticating the authentication article includes: providing the authentication article; subjecting the analytes to a probe stimulus; acquiring a response from the plurality of analytes in response to being subjected to the probe stimulus; and determining whether the response is the authentication signature to authenticate the, wherein the authentication article is not authenticated if the response is not the authentication signature for the array.

Abstract: An authentication article includes: a substrate including: a first surface; a second surface disposed laterally to the first surface and at a depth below the first surface; and a plurality of indentations including the depth at the second surface of the substrate; and an array disposed on the substrate and including a plurality of analytes, the analytes being disposed in the indentations at a depth below a first surface of the substrate and provided to emit an authentication signature in response to being subjected to a probe stimulus. A process for authenticating the authentication article includes: providing the authentication article; subjecting the analytes to a probe stimulus; acquiring a response from the plurality of analytes in response to being subjected to the probe stimulus; and determining whether the response is the authentication signature to authenticate the, wherein the authentication article is not authenticated if the response is not the authentication signature for the array.

Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.

Abstract: A method for manufacturing a semiconductor device. The method comprises forming a metal layer on a silicon-containing layer located on a semiconductor substrate. The method also comprises reacting a portion of the metal layer with the silicon-containing layer to form a metal silicide layer. The method further comprises removing an unreacted portion of the metal layer on the metal silicide layer by a removal process. The removal process includes delivering a flow of an acidic solution to a surface of the unreacted portion of the metal layer, wherein the acidic solution delivered to the surface is substantially gas-free.

Abstract: A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.

Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

Abstract: Exemplary embodiments provide IC CMOS devices having dual stress layers and methods for their manufacture using a buffer layer stack between the two types of the stress layers. The buffer layer stack can include multiple buffer layers formed between a first type stress layer (e.g., a tensile stress layer) and a second type stress layer (e.g., a compressive stress layer) during the CMOS fabrication. Specifically, the buffer layer stack can be formed after the etching process of the first type stress layer but prior to the etching process of the second type stress layer, and thus to protect the etched first type stress layer during the subsequent etching process of the overlaid second type stress layer. In addition, a portion of the buffer layer stack can be formed between, for example, the compressive stress layer and the underlying PMOS device to enhance their adhesion.

Abstract: A method for manufacturing a semiconductor device. The method comprises forming a metal layer on a silicon-containing layer located on a semiconductor substrate. The method also comprises reacting a portion of the metal layer with the silicon-containing layer to form a metal silicide layer. The method further comprises removing an unreacted portion of the metal layer on the metal silicide layer by a removal process. The removal process includes delivering a flow of an acidic solution to a surface of the unreacted portion of the metal layer, wherein the acidic solution delivered to the surface is substantially gas-free.

Abstract: A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.

Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.

Abstract: The present invention is directed, in general, to a chemical mechanical polishing pad comprising a polishing body and a backing material coupled to the polishing body. The polishing body comprising a compacted thermoplastic foam substrate, wherein the compacted thermoplastic foam substrate has a density that is as at least about 1.1 times greater than an uncompacted thermoplastic foam substrate density. Other aspects of the invention comprise a method for manufacturing the above-described chemical mechanical polishing pad and chemical mechanical polishing apparatus comprising the chemical mechanical polishing pad.

Abstract: The present invention is directed, in general, to a method of polishing a surface on substrates, such as semiconductor wafers and, more specifically, to a polishing pad suitable for this purpose. The polishing pad comprises a polishing body that includes a cross-linked polymer material, and may be incorporated into a polishing apparatus. Polishing includes positioning the substrate containing at least one layer against the polishing body and polishing the layer.

Abstract: The present invention provides, chemical mechanical polishing pad with improved polishing properties and longevity for polishing semiconductor wafers. The polishing pad comprises a thermoplastic backing film and a pressure sensitive adhesive coupled to the thermoplastic backing film. The pressure sensitive adhesive is configured to couple a chemical mechanical polishing pad to a polishing platen. The pressure sensitive adhesive is further configured to provide an interface capable of substantially preventing delamination of the polishing pad from the polishing platen for at least about 4 days exposure to a polishing slurry medium having a pH of about 4 or higher.

Abstract: The present invention is directed to a method for preparing a polymer for chemical mechanical polishing of a semiconductor substrate. The method comprises providing a thermoplastic foam substrate and exposing the substrate to an initial plasma reactant to produce a modified surface thereon. The method also includes exposing the modified surface to a secondary plasma reactant to create a grafted surface on the modified surface. An electrode temperature is maintained between about 20° C. and about 100° C. during the exposures of the substrate and the modified surface.

Abstract: The present invention is directed, in general, to a method of planarizing a surface on a semiconductor wafer and, more specifically, to a method of altering the properties of polishing pads to improve thermal management during chemical-mechanical planarization, the resulting heat conductive pad and a polishing apparatus that includes the pad. The pad includes a polishing body composed of a thermoconductive polymer comprising an substrate and filler particle containing a Group II salt and within the substrate.

Abstract: The present invention provides, chemical mechanical polishing pad with improved polishing properties and longevity for polishing semiconductor wafers. The polishing pad comprises a thermoplastic backing film and a pressure sensitive adhesive coupled to the thermoplastic backing film. The pressure sensitive adhesive is configured to couple a chemical mechanical polishing pad to a polishing platen. The pressure sensitive adhesive is further configured to provide an interface capable of substantially preventing delamination of the polishing pad from the polishing platen for at least about 4 days exposure to a polishing slurry medium having a pH of about 4 or higher.

Abstract: The present invention is directed, in general, to packaged polishing pads for chemical mechanical polishing of semiconductor wafers and integrated circuits. More specifically, the invention is directed to a method of preparing and packing the pad and the packaging therefor. Prior to placing the pad on a platen and polishing with the pad, a polishing pad having an hygroscopic absorbency is soaked with an aqueous media for a time sufficient to equilibrate the pad. The pad maybe packaged by placement in a sealable moisture tight package after soaking or before soaking along with a sufficient quantity of aqueous media to allow the pad to equilibrate.