Patents by Inventor Yayoi Nakamura

Yayoi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6624856
    Abstract: According to the present invention, a channel protection film is formed a little smaller in area than the gate electrode formed of a shielding metal film. A semiconductor thin film is formed such that the thickness is set not less than 200 Å and less than 400 Å. A distance A between the edge of the gate electrode in the channel length direction and the edge of the channel protection film is set around 0.2-1.2 &mgr;m, and a distance B between the edge of the gate electrode in the channel width direction and the edge of the channel protection film is set around 1-2 &mgr;m. With this constitution, the leak current of the thin film transistor due to the light irradiation can be reduced.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: September 23, 2003
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hitoshi Watanabe, Shinichi Shimomaki, Yayoi Nakamura
  • Publication number: 20030093428
    Abstract: Disclosed is an interactive browsing system for acquiring target information in a prescribed information page, which exists at a prescribed site on a network, in response to a request from a user. The system includes a knowledge management unit for storing knowledge necessary to acquire a keyword of a utilizable information page; a human-like agent for analyzing a request, which the user has entered, using the knowledge, and extracting a keyword conforming to the user request; and a browser (data analyzing unit) for acquiring desired target information from the network using the keyword, and outputting this target information to an input/output unit in an appropriate format.
    Type: Application
    Filed: April 3, 2002
    Publication date: May 15, 2003
    Inventors: Shingo Suzumori, Yayoi Nakamura, Ryuji Sakunaga, Hiroshi Sugitani
  • Patent number: 6480435
    Abstract: A semiconductor memory device includes control circuits for respectively controlling operation timings of respective sense amplifiers related to an odd-numbered bit line pair and related to an even-numbered bit line pair. The control circuits thus allow respective sense amplifiers provided for bit line pairs adjacent to each other to operate at different timings respectively.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: November 12, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yayoi Nakamura, Takashi Itou
  • Publication number: 20020101774
    Abstract: A semiconductor memory device includes control circuits for respectively controlling operation timings of respective sense amplifiers related to an odd-numbered bit line pair and related to an even-numbered bit line pair. The control circuits thus allow respective sense amplifiers provided for bit line pairs adjacent to each other to operate at different timings respectively.
    Type: Application
    Filed: August 17, 2001
    Publication date: August 1, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yayoi Nakamura, Takashi Itou
  • Publication number: 20020057391
    Abstract: There is disclosed an active matrix liquid crystal display apparatus in which a data signal line is disposed apart from a pixel electrode, a gate insulating film is disposed between the data signal line and an extending portion of an auxiliary capacity line, the extending portion is superposed upon a peripheral portion of the pixel electrode, and a parasitic capacity Cds between the pixel electrode and the data signal line is reduced.
    Type: Application
    Filed: November 8, 2001
    Publication date: May 16, 2002
    Applicant: Casio Computer Co., Ltd.
    Inventor: Yayoi Nakamura
  • Patent number: 6349066
    Abstract: An output circuit (6) of a DRAM (semiconductor storage device) is provided with a refresh monitor circuit which is substantially composed of a NAND gate (NA1), an AND gate (A1), Pch-Tr2 and Nch-Tr4. The TMSELF signal (test mode signal) and the int. ZRAS signal (internal signal for provoking a refreshing action) are inputted into the refresh monitor circuit. The refresh monitor circuit outputs a monitoring signal, which has a wave form as same as that of the int. ZRAS signal, to an output node (DQ) of the output circuit (6), when the TMSELF signal has become H during the self refresh process. The refresh monitor circuit can monitor the int. ZRAS signal on the basis of the monitoring signal.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: February 19, 2002
    Assignee: Mitsubishi Denki Kabuhsiki Kaisha
    Inventor: Yayoi Nakamura
  • Publication number: 20020003589
    Abstract: According to the present invention, a channel protection film is formed a little smaller in area than the gate electrode formed of a shielding metal film. A semiconductor thin film is formed such that the thickness is set not less than 200 Å and less than 400 Å. A distance A between the edge of the gate electrode in the channel length direction and the edge of the channel protection film is set around 0.2-1.2 &mgr;m, and a distance B between the edge of the gate electrode in the channel width direction and the edge of the channel protection film is set around 1-2 &mgr;m. With this constitution, the leak current of the thin film transistor due to the light irradiation can be reduced.
    Type: Application
    Filed: July 3, 2001
    Publication date: January 10, 2002
    Applicant: Casio Computer Co. , Ltd.
    Inventors: Hitoshi Watanabe, Shinichi Shimomaki, Yayoi Nakamura
  • Publication number: 20010025306
    Abstract: When a session management apparatus receives a process request containing the identifier of a session using a plurality of media such as e-mail, WEB, voice, etc., it converts the identifier into uniformly available data to perform session management such as a start of a session, session identity management, a disconnection of the session, etc.
    Type: Application
    Filed: January 3, 2001
    Publication date: September 27, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Nobuyoshi Ninokata, Shingo Suzumori, Yayoi Nakamura
  • Patent number: 6201748
    Abstract: In an output buffer of a DRAM, a level shifter outputs a step-up potential responsively when an internal data signal goes low or a test mode signature goes high. An N-channel MOS transistor is rendered conductive in response to the step-up potential from the level shifter, and sets a data input terminal to a power supply potential. The internal data signal and the test mode signature share the level shifter and the N-channel MOS transistor, and hence the layout area can be small and a high-level test mode signature can be output.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: March 13, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yayoi Nakamura, Koji Tanaka, Yasuhiko Tsukikawa
  • Patent number: 6118325
    Abstract: A plurality of output transistors for an output buffer of a semiconductor device are provided in parallel. Potentials to be applied to gates of output transistors are set to different levels upon conduction of the output transistors. By sequentially rendering the transistors conductive in the order of increasing voltage during conduction, rapid flow of a large amount of current is prevented, thereby reducing ringing. More preferably, the transistors are increased in size according to the order of conduction of the output transistors.
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: September 12, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yayoi Nakamura
  • Patent number: 4346169
    Abstract: Mutants of the genus Bervibacterium or Corynebacterium are given resistance to keto-malonic acid, fluoro-malonic acid, monofluoro-acetic acid or aspartate antagonist and used to produce L-arginine by aerobic fermentation.
    Type: Grant
    Filed: September 15, 1980
    Date of Patent: August 24, 1982
    Assignee: Ajinomoto Company, Incorporated
    Inventors: Kunihiko Akashi, Yayoi Nakamura, Takayasu Tsuchida, Hiroe Yoshii, Shigeho Ikeda