Patents by Inventor Yazhou Zu
Yazhou Zu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230168919Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media for performing preflight checks of a distributed computing system, are described. In one aspect, a method includes assigning a computing workload to a first subset of hardware accelerator machines each having one or more hardware accelerators. A preflight check on the first subset is performed before performing the computing workload to verify the functionality of each machine in the first subset. For each hardware accelerator machine of the first subset, a program code package is installed, including a task action based at least in part on characteristics of the computing workload. The task action including a sequence of operations is performed on the hardware accelerator machine to determine whether the task action fails. Whenever the task action fails, the computing workload is re-assigned to a second subset of hardware accelerator machines different from the first subset.Type: ApplicationFiled: December 1, 2021Publication date: June 1, 2023Inventors: Jiafan Zhu, Jianqiao Liu, Xiangyu Dong, Xiao Zhang, Jikai Tang, Kexin Yang, Yong Zhao, Alireza Ghaffarkhah, Arash Rezaei, Dayou Du, Yazhou Zu, Xiangling Kong, Hoang-Vu Dang, Alexander Vadimovich Kolbasov
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Patent number: 11630152Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.Type: GrantFiled: March 4, 2021Date of Patent: April 18, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu
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Publication number: 20220114440Abstract: This disclosure generally provides solutions for improving the performance of a custom-built, packet-switched, TPU accelerator-side communication network. Specifically a set of solutions to improve the flow-control behavior by tuning the packet buffer queues in the on-chip router in the distributed training supercomputer network are described.Type: ApplicationFiled: December 29, 2020Publication date: April 14, 2022Inventors: Xiangyu Dong, Kais Belgaied, Yazhou Zu
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Publication number: 20210270897Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.Type: ApplicationFiled: March 4, 2021Publication date: September 2, 2021Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu
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Patent number: 11002791Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.Type: GrantFiled: May 14, 2020Date of Patent: May 11, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu
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Publication number: 20200300913Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.Type: ApplicationFiled: May 14, 2020Publication date: September 24, 2020Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu
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Patent number: 10690723Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.Type: GrantFiled: April 30, 2019Date of Patent: June 23, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu
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Publication number: 20200158782Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.Type: ApplicationFiled: April 30, 2019Publication date: May 21, 2020Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu
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Patent number: 10649514Abstract: A method and apparatus for managing processing power determine a supply voltage to supply to a processing unit, such as a central processing unit (CPU) or graphics processing unit (GPU), based on temperature inversion based voltage, frequency, temperature (VFT) data. The temperature inversion based VFT data includes supply voltages and corresponding operating temperatures that cause the processing unit's transistors to operate in a temperature inversion region. In one example, the temperature inversion based VFT data includes lower supply voltages and corresponding higher temperatures in a temperature inversion region of a processing unit. The temperature inversion based VFT data is based on an operating frequency of the processing unit. The apparatus and method adjust a supply voltage to the processing unit based on the temperature inversion based VFT data.Type: GrantFiled: September 23, 2016Date of Patent: May 12, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Wei Huang, Yazhou Zu, Indrani Paul
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Patent number: 10365327Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.Type: GrantFiled: October 18, 2017Date of Patent: July 30, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu
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Publication number: 20190113572Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.Type: ApplicationFiled: October 18, 2017Publication date: April 18, 2019Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu
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Publication number: 20180088606Abstract: A method and apparatus for managing processing power determine a supply voltage to supply to a processing unit, such as a central processing unit (CPU) or graphics processing unit (GPU), based on temperature inversion based voltage, frequency, temperature (VFT) data. The temperature inversion based VFT data includes supply voltages and corresponding operating temperatures that cause the processing unit's transistors to operate in a temperature inversion region. In one example, the temperature inversion based VFT data includes lower supply voltages and corresponding higher temperatures in a temperature inversion region of a processing unit. The temperature inversion based VFT data is based on an operating frequency of the processing unit. The apparatus and method adjust a supply voltage to the processing unit based on the temperature inversion based VFT data.Type: ApplicationFiled: September 23, 2016Publication date: March 29, 2018Inventors: Wei Huang, Yazhou Zu, Indrani Paul