Patents by Inventor Ye Chao Li

Ye Chao Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for performing deep n-typed well-correlated (DNW-correlated) antenna rule check of integrated circuit and semiconductor structure complying with DNW-correlated antenna rule
    Patent number: 9607123
    Abstract: A semiconductor monitoring device includes a substrate, a die seal ring formed on the substrate, a deep n-typed well formed in the substrate under the die seal ring, and a monitoring device electrically connected to the die seal ring. The monitoring device is formed in a scribe line region defined on the substrate. A width of the deep n-typed well is larger than a width of the die seal ring.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: March 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Xing Hua Zhang, Chi-Fa Ku, Hong Liao, Ye Chao Li, Hui Yang
  • MONITORING SEMICONDUCTOR DEVICE, METHOD FOR PERFORMING DEEP N-TYPED WELL-CORRELATED (DNW-CORRELATED) ANTENNA RULE CHECK OF INTEGRATED CIRCUIT AND SEMICONDUCTOR STRUCTURE COMPLYING WITH DNW-CORRELATED ANTENNA RULE
    Publication number: 20160211187
    Abstract: A semiconductor monitoring device includes a substrate, a die seal ring formed on the substrate, a deep n-typed well formed in the substrate under the die seal ring, and a monitoring device electrically connected to the die seal ring. The monitoring device is formed in a scribe line region defined on the substrate. A width of the deep n-typed well is larger than a width of the die seal ring.
    Type: Application
    Filed: January 16, 2015
    Publication date: July 21, 2016
    Inventors: Xing Hua Zhang, Chi-Fa Ku, Hong Liao, Ye Chao Li, Hui Yang
  • Semiconductor device and method for fabricating the same
    Patent number: 9331200
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; and forming a first epitaxial layer, a second epitaxial layer, and a silicide layer in the substrate adjacent to the gate structure. Preferably, the first epitaxial layer, the second epitaxial layer, and the silicide layer comprise SiGeSn.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: May 3, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lanxiang Wang, Hong Liao, Chao Jiang, Duan Quan Liao, Ye Chao Li