Patents by Inventor Yeeheng Lee
Yeeheng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10424654Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.Type: GrantFiled: June 27, 2018Date of Patent: September 24, 2019Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Wenjun Li, Paul Thorup, Hong Chang, Yeeheng Lee, Yang Xiang, Jowei Dun, Hongyong Xue, Yiming Gu
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Patent number: 10297594Abstract: A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.Type: GrantFiled: August 6, 2015Date of Patent: May 21, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Yeeheng Lee, Jongoh Kim, Hong Chang
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Patent number: 10192982Abstract: A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device includes a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each trench has a first dimension (depth), a a second dimension (width) and a third dimension (length). The body region is of opposite conductivity type to the lightly and heavily doped layers. An opening is formed between first and second trenches through an upper portion of the source region and a body contact region to the body region. A deep implant region of the second conductivity type is formed in the lightly doped layer below the body region. The deep implant region is vertically aligned to the opening and spaced away from a bottom of the opening.Type: GrantFiled: August 18, 2017Date of Patent: January 29, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Hamza Yilmaz, Daniel Ng, Daniel Calafut, Madhur Bobde, Anup Bhalla, Ji Pan, Yeeheng Lee, Jongoh Kim
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Publication number: 20180323282Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.Type: ApplicationFiled: June 27, 2018Publication date: November 8, 2018Applicant: Alpha & Omega Semiconductor, IncorporatedInventors: Wenjun Li, Paul Thorup, Hong Chang, Yeeheng Lee, Yang Xiang, Jowei Dun, Hongyong Xue, Yiming Gu
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Patent number: 10020380Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.Type: GrantFiled: January 23, 2015Date of Patent: July 10, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Wenjun Li, Paul Thorup, Hong Chang, Yeeheng Lee, Yang Xiang, Jowei Dun, Hongyong Xue, Yiming Gu
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Patent number: 10008579Abstract: Schottky structure fabrication includes forming two trenches in a semiconductor material. The trenches are separated from each other by a mesa. Sidewalls and a bottom surface of the trenches are lined with a dielectric material. A conductive material is disposed in the trenches lining the dielectric material on the sidewalls and the bottom surface. The conductive material on the bottom surface of the trenches is removed so that a first portion of conductive material remains on a first sidewall of each trench, and a second portion of conductive material remains on a second sidewall of each trench. The first and second portions of conductive material are electrically isolated from each other. The space between the first and second portions of the conductive material is filled with a trench filling insulator material and a Schottky contact is formed between the outermost sidewalls of the two trenches.Type: GrantFiled: June 17, 2016Date of Patent: June 26, 2018Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Daniel Calafut, Yeeheng Lee
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Patent number: 9865694Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.Type: GrantFiled: January 23, 2017Date of Patent: January 9, 2018Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Yeeheng Lee, Lingpeng Guan, Hongyong Xue, Yiming Gu, Yang Xiang, Terence Huang, Sekar Ramamoorthy, Wenjun Li, Hong Chang, Madhur Bobde, Paul Thorup, Hamza Yilmaz
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Publication number: 20170373185Abstract: A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device includes a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each trench has a first dimension (depth), a a second dimension (width) and a third dimension (length). The body region is of opposite conductivity type to the lightly and heavily doped layers. An opening is formed between first and second trenches through an upper portion of the source region and a body contact region to the body region. A deep implant region of the second conductivity type is formed in the lightly doped layer below the body region. The deep implant region is vertically aligned to the opening and spaced away from a bottom of the opening.Type: ApplicationFiled: August 18, 2017Publication date: December 28, 2017Inventors: Hamza Yilmaz, Daniel Ng, Daniel Calafut, Madhur Bobde, Anup Bhalla, Ji Pan, Yeeheng Lee, Jongoh Kim
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Patent number: 9818829Abstract: Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top electrode in its upper portions. The bottom electrode and the top electrode are separated by an insulating material. A contact structure filled with conductive materials is formed in each trench in an area outside of an active region of the device to connect the top electrode and the bottom electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.Type: GrantFiled: July 19, 2016Date of Patent: November 14, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Yeeheng Lee, Sik Lui, Jongoh Kim, Hong Chang, Madhur Bobde, Lingpeng Guan, Hamza Yilmaz
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Patent number: 9748375Abstract: A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.Type: GrantFiled: March 4, 2016Date of Patent: August 29, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Hamza Yilmaz, Daniel Ng, Daniel Calafut, Madhur Bobde, Anup Bhalla, Ji Pan, Yeeheng Lee, Jongoh Kim
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Patent number: 9741808Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.Type: GrantFiled: March 4, 2016Date of Patent: August 22, 2017Assignee: Alpha and Omage Semiconductor Inc.Inventors: Yeeheng Lee, Lingpeng Guan, Hongyong Xue, Yiming Gu, Yang Xiang, Terence Huang, Sekar Ramamoorthy, Wenjun Li, Hong Chang, Madhur Bobde, Paul Thorup, Hamza Yilmaz
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Patent number: 9673289Abstract: A power MOSFET device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the active trench by a liner oxide layer having a first thickness, and a termination trench formed in the semiconductor layer apart from the active trench and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the termination trench by the liner oxide layer having a second thickness. In one embodiment, the second thickness is greater than the first thickness. In another embodiment, the trench gate in each of the active trench and the termination trench is formed as a single polysilicon layer.Type: GrantFiled: October 12, 2015Date of Patent: June 6, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Daniel Calafut, Madhur Bobde, Yeeheng Lee, Hong Chang
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Publication number: 20170133473Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.Type: ApplicationFiled: January 23, 2017Publication date: May 11, 2017Inventors: Yeeheng Lee, Lingpeng Guan, Hongyong Xue, Yiming Gu, Yang Xiang, Terence Huang, Sekar Ramamoorthy, Wenjun Li, Hong Chang, Madhur Bobde, Paul Thorup, Hamza Yilmaz
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Patent number: 9647059Abstract: This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types.Type: GrantFiled: June 8, 2014Date of Patent: May 9, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Lingping Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
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Publication number: 20170125531Abstract: Semiconductor device fabrication method and devices are disclosed. The semiconductor power device is formed on a semiconductor substrate having a plurality of trench transistor cells each having a trench gate. Each of the trench gates having a thicker bottom oxide (TBO) formed by a REOX process on a polysilicon layer deposited on a bottom surface of the trenches.Type: ApplicationFiled: February 4, 2014Publication date: May 4, 2017Inventors: Yeeheng Lee, Xiaobin Wang
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Publication number: 20170125514Abstract: This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types.Type: ApplicationFiled: June 8, 2014Publication date: May 4, 2017Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
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Patent number: 9627526Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.Type: GrantFiled: March 24, 2014Date of Patent: April 18, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Yeeheng Lee, Yongping Ding, Xiaobin Wang
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Patent number: 9595587Abstract: Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top electrode in its upper portions. The bottom electrode and the top electrode are separated by an insulating material. A contact structure filled with conductive materials is formed in each trench in an area outside of an active region of the device to connect the top electrode and the bottom electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.Type: GrantFiled: April 23, 2014Date of Patent: March 14, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Yeeheng Lee, Sik Lui, Jongoh Kim, Hong Chang, Madhur Bobde, Lingpeng Guan, Hamza Yilmaz
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Publication number: 20170069750Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.Type: ApplicationFiled: March 24, 2014Publication date: March 9, 2017Applicant: ALPHA & OMEGA SEMICONDUCTOR INCORPORATEDInventors: Yeeheng Lee, Yongping Ding, Xiaobin Wang
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Publication number: 20160372542Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.Type: ApplicationFiled: July 12, 2014Publication date: December 22, 2016Inventors: Yeeheng Lee, Madhur Bobde, Yongping Ding, Jongoh Kim, Anup Bhalla