Abstract: A scaleable laser and control unit (58) is used to differentially heat portions of a semiconductor substrate (40) during downstream etching. Such differential heating provides a differential etch rate for each portion heated resulting in improved uniformity and reduced etch induced surface damage. An etching chamber (50) capable of containing the downstream plasma and providing a direct line of sight between the substrate (40) and the scanable laser unit (58) is provided. In addition, the system provides for dynamic updating of the process by in situ etch rate and temperature measurements.

Abstract: A distributed polishing head assembly (17) has a flexible membrane (14), and a plurality of periodic polishing pads (12) that are attached to the flexible membrane (14). The polishing pads (12) are made from a flat semiconductor wafer that has been sawed into small pieces. The polishing head is rubbed against a semiconductor wafer (10) in order to planarize the wafer (10).

Abstract: An integrated fluid dispense apparatus (10) suitable for delivering ultrapure fluids. The fluid is confined to a nonrigid hermetic fluid delivery apparatus (10). A pumping mechanism (11) pumps fluids in precise volumes and flow rates. A moisturizing dispense nozzle (12) provides a saturated vapor atmosphere at the nozzle tip to prevent the fluid from drying during non-dispense periods.

Abstract: A method is provided for selectively etching materials on a semiconductor wafer (10, 30) that have similar etch rates. The semiconductor wafer (10, 30) is provided with at least a first layer. An etch mask is provided on the first layer. The layer with the etch mask (13) is partially etched to a predetermined point. A polymer film (21, 38) is deposited on the partially etched layer. The polymer film (21, 38) is etched in an anisotropic manner creating open or clear areas (14, 34) in the horizontal polymer film, while leaving polymer coating (22, 37) on vertical walls (12, 36). The open areas (14, 34) are chemically etched, while the remaining polymer coating (22, 37) on the vertical walls (12, 36) protects the vertical walls (12, 36) from being chemically etched. This method also protects the top surface of the semiconductor wafer.

Abstract: A method for the selective deposition of metals in semiconductor device manufacturing wherein a wafer surface is subjected to a hydrogen species that reduces oxidation on conducting materials while also removing impurities from non-conducting materials. Metals are then selectively deposited upon the conducting materials and not upon the non-conducting materials. It should be understood that the hydrogen treatment step and the selective metal deposition step may be performed simultaneously or by using two separate processing steps.

Abstract: A magnetically enhanced plasma etch reactor utilizing electromagnets for rotation and translational scans of a linear magnetic field in a reaction chamber to produce a dense and uniform plasma for the etch of a workpiece.

Abstract: A process is described for producing semiconductor devices using a single master mask which determines the lateral dimensions of certain critical device and/or device contact regions in combination with a surrounding isolation wall. Various dielectric layers and isotropic and anisotropic etching steps are utilized in combination with a series of block-out masks to permit etching of a trench in the location of the peripheral isolation wall image in the master mask which is subsequently filled with a dielectric-semiconductor combination. For the case of a vertical bipolar transistor, a base region is implanted using an oversize selector mask. Successive block-out masks are then used to select the particular openings in the master mask which will form the base contact, the emitter and emitter contact and the collector contact. No precision alignments are required between the master mask and the selector or block-out masks.

Abstract: A polyimide-oxide-polyimide integrated circuit structure is utilized in the process for forming openings having tapered sidewalls and predetermined controlled sizes. At least one opening size is replicated and transferred to an exposed surface in a underlying surface of the structure by first forming a thick layer of oxide over the first cured polyimide layer, anisotropically etching the thick layer of oxide to form an opening of predetermined size therethrough to the surface of the first cured polyimide layer. Next, the first layer of cured polyimide is isotropically etched to form an opening therethrough of substantially said predetermined size and exposing a portion of a thin layer of oxide underlying the first layer of cured polyimide. The thin layer of oxide is then anisotropically etched using the thick layer of oxide as an etch mask to expose an opening of said predetermined size on a surface of a second layer of cured polyimide.

Abstract: A process is disclosed for fabricating semiconductor devices, and especially for fabricating semiconductor devices having multiple levels of metallization separated by polyimide or other organic materials. The process avoids the sputter etching and redeposition of the lower metal layer during reactive ion etching of openings through the organic layer. Sequential layers overlying the first layer of metallization include a layer of oxide, a layer of organic material, and a second layer of oxide. The second layer of oxide functions as a hard mask for patterning the organic material. The first layer of oxide acts as an etch stop and protective layer to prevent attack of the underlying metal during reactive ion etching of the organic layer. The first layer of oxide is of limited areal extent to avoid subsequent problems with the organic layer.

Abstract: A method is disclosed for forming openings in polyimide layers and for thereby forming semiconductor devices. The method allows for the forming of openings having tapered side walls and precise dimensional control. First and second layers of polyimide are sequentially formed on a surface. The first layer, in contact with the surface, is fully cured while the second layer is only partially cured. Overlying the second layer is a masking layer which can alternatively be an inorganic material or a resist material. A pattern is formed in the masking layer to expose portions of the upper polyimide layer. The pattern includes openings of predetermined size having a precise critical dimension. Using the patterned masking layer as an etch mask the upper layer of polyimide is isotropically etched in an etchent which etches the partially cured polyimide but which does not etch the fully cured underlying polyimide.