Patents by Inventor Yefim-Haim Fefer

Yefim-Haim Fefer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9097758
    Abstract: An integrated circuit device comprising a semiconductor die contained in a package. The integrated circuit device includes one or more internal connection verification modules for asserting a poor connection signal for the test apparatus in response to a voltage difference between a voltage at a corresponding internal power supply node and a reference voltage, the voltage difference being indicative of a poor connection of power supply to one of power supply terminals on the package. The test apparatus can include an indicator or a sorting element for rejecting or accepting the integrated circuit device in response to logic signals indicative of the presence or absence of a defect accompanied by non-assertion of the poor connection signal, and for processing the integrated circuit device distinctively in response to assertion of the poor connection signal.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: August 4, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yefim-Haim Fefer, Sergey Sofer, Boris Zapesochini
  • Patent number: 8896341
    Abstract: An integrated circuit device comprising at least one calibration module for calibrating an impedance of at least one on-die interconnect line driver in order to adaptively match an impedance between the at least one on-die interconnect line driver and at least one on-die interconnect line conjugated thereto. The at least one calibration module is arranged to receive an indication of an output signal of the at least one line driver, compare the received indication of an output signal to a reference signal and detect a presence or an absence of a voltage overshoot of the output signal of the at least one line driver, and upon detection of a presence or an absence of a voltage overshoot of the output signal of the at least one line driver, cause the adjustment of power supply of the at least one line driver, to be decreased or increased correspondingly.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: November 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sergey Sofer, Yefim-Haim Fefer, Pavel Livshits
  • Patent number: 8737029
    Abstract: An integrated circuit, comprises a power supply node being connectable to a voltage supply (Vdd); a ground node connectable to ground (GND); and an electrostatic discharge protection structure for diverting an electrostatic discharge away from protected parts of the integrated circuit. A gated domain is present which is supply gated and/or ground gated with respect to the power supply node and/or the ground node, as well as a gating switch for gating the gated domain relative to the power supply node and/or the ground node. The gating switch enables in a connecting state, and in a disconnecting state inhibits, an electrical connection between the gated domain and at least one of: the power supply node and the ground node. The integrated circuit includes ESD gating control circuitry for controlling in case of an electrostatic discharge event the gated domain to be electrically connected to the power supply node and/or the ground node.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: May 27, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sergey Sofer, Yefim-Haim Fefer, Dov Tzytkin
  • Patent number: 8531197
    Abstract: An integrated circuit die comprises an electronic circuit and one or more output ports for outputting signals from the die via an external impedance, to a load, external from the die. The output port is connected to the electronic circuit. The die is further provided with an on-die sampling oscilloscope circuit connected to the output port, for measuring a waveform of the outputted signals.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: September 10, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yefim-Haim Fefer, Valery Neiman, Sergey Sofer
  • Publication number: 20130038373
    Abstract: An integrated circuit device comprising at least one calibration module for calibrating an impedance of at least one on-die interconnect line driver in order to adaptively match an impedance between the at least one on-die interconnect line driver and at least one on-die interconnect line conjugated thereto. The at least one calibration module is arranged to receive an indication of an output signal of the at least one line driver, compare the received indication of an output signal to a reference signal and detect a presence or an absence of a voltage overshoot of the output signal of the at least one line driver, and upon detection of a presence or an absence of a voltage overshoot of the output signal of the at least one line driver, cause the adjustment of power supply of the at least one line driver, to be decreased or increased correspondingly.
    Type: Application
    Filed: June 10, 2010
    Publication date: February 14, 2013
    Applicant: Freescale Semiconductor , Inc.
    Inventors: Sergey Sofer, Yefim-Haim Fefer, Pavel Livshits
  • Patent number: 8368383
    Abstract: A device and a method for testing a variable digital delay line that includes multiple taps. The method includes providing, an input signal to the variable digital delay line and finding, for each tap out of a group of tested taps of the variable digital delay line, a variable delay unit configuration that provides a delay that is closest to a delay introduced by the tap; wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: February 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yefim-Haim Fefer, Mikhail Bourgart, Segey Sofer, Yoav Weizman
  • Publication number: 20120169411
    Abstract: A device that includes at least one current consuming component. The device is characterized by including a compensation circuit adapted to compare between a voltage level at a sensing point within an integrated circuit and between a reference voltage derived from a voltage peak level at the sensing point; and to selectively increase the voltage at the sensing point in response to the comparison. A method for compensating for voltage drops in an integrated circuit, the method includes providing at least a first supply voltage to an integrated circuit; the method is characterized by including: comparing between a voltage level at a sensing point within an integrated circuit to a reference voltage derived from a voltage peak level at the sensing point; and selectively increasing the voltage at the sensing point in response to the comparison.
    Type: Application
    Filed: November 15, 2005
    Publication date: July 5, 2012
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yefim-Haim Fefer, Sergey Sofer
  • Publication number: 20120050926
    Abstract: An integrated circuit, comprises a power supply node being connectable to a voltage supply (Vdd); a ground node connectable to ground (GND); and an electrostatic discharge protection structure for diverting an electrostatic discharge away from protected parts of the integrated circuit. A gated domain is present which is supply gated and/or ground gated with respect to the power supply node and/or the ground node, as well as a gating switch for gating the gated domain relative to the power supply node and/or the ground node. The gating switch enables in a connecting state, and in a disconnecting state inhibits, an electrical connection between the gated domain and at least one of: the power supply node and the ground node. The integrated circuit includes ESD gating control circuitry for controlling in case of an electrostatic discharge event the gated domain to be electrically connected to the power supply node and/or the ground node.
    Type: Application
    Filed: May 14, 2009
    Publication date: March 1, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Sergey Sofer, Yefim-Haim Fefer, Dov Tzytkin
  • Publication number: 20120038367
    Abstract: An integrated circuit device comprising a semiconductor die contained in a package. The integrated circuit device includes one or more internal connection verification modules for asserting a poor connection signal for the test apparatus in response to a voltage difference between a voltage at a corresponding internal power supply node and a reference voltage, the voltage difference being indicative of a poor connection of power supply to one of power supply terminals on the package. The test apparatus can include an indicator or a sorting element for rejecting or accepting the integrated circuit device in response to logic signals indicative of the presence or absence of a defect accompanied by non-assertion of the poor connection signal, and for processing the integrated circuit device distinctively in response to assertion of the poor connection signal.
    Type: Application
    Filed: March 31, 2009
    Publication date: February 16, 2012
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yefim-Haim Fefer, Sergey Sofer, Boris Zapesochini
  • Publication number: 20110121818
    Abstract: An integrated circuit die comprises an electronic circuit and one or more output ports for outputting signals from the die via an external impedance, to a load, external from the die. The output port is connected to the electronic circuit. The die is further provided with an on-die sampling oscilloscope circuit connected to the output port, for measuring a waveform of the outputted signals.
    Type: Application
    Filed: July 17, 2008
    Publication date: May 26, 2011
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yefim-Haim Fefer, Valery Neiman, Sergey Sofer
  • Publication number: 20100072979
    Abstract: A device and a method for testing a variable digital delay line that includes multiple taps. The method includes providing, an input signal to the variable digital delay line and finding, for each tap out of a group of tested taps of the variable digital delay line, a variable delay unit configuration that provides a delay that is closest to a delay introduced by the tap; wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit.
    Type: Application
    Filed: January 5, 2007
    Publication date: March 25, 2010
    Applicant: Freescale Semiconductor,Inc
    Inventors: Yefim-Haim Fefer, Mikhail Bourgart, Segey Sofer, Yoav Weizman