Patents by Inventor Yehuda Yitschak

Yehuda Yitschak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11917041
    Abstract: Communication in an asymmetric multiengine system is handled using engine routing tables defining subsets of engines to control engine-to-engine connection mapping. Local devices perform an engine selection process that includes selecting an engine routing table based on a number of remote engines in a remote device and selecting an engine set from the selected table based on an identifier of the remote device. A connection to the remote device is created using the engines identified in the selected engine set.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: February 27, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Saleh Abd-Alhaleem, Leah Shalev, Hani Ayoub, Avigdor Segal, Shadi Ammouri, Yossi Leybovich, Yehuda Yitschak
  • Patent number: 9143793
    Abstract: Video processing system, computer program product and method for managing an exchange of information between a memory unit and a decoder, the method includes: (a) retrieving, from the memory unit, a first non-zero data structure that comprises only non-zero first transform coefficient groups; wherein first transform coefficient groups are associated with a first quality level; (b) retrieving, from the memory unit, second layer information; (c) processing, by the video decoder, the second layer information and the first non-zero data structure to provide second transform coefficient groups; (c) generating, by the video decoder, a second non-zero data structure that comprises only non-zero second transform coefficient groups; wherein the second non-zero data structure is associated with a second quality level that is higher than the first quality level; (d) generating second non-zero indicators that are indicative of non-zero transform coefficient groups, wherein the second non-zero data structure is associated
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: September 22, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Erez Steinberg, Moshe Nakash, Yehuda Yitschak
  • Patent number: 8737475
    Abstract: A method of encoding a video frame is disclosed in which video slices of the video frame are initially encoded in parallel using both interframe encoding and intraframe encoding. Then, after a first predetermined minimum amount of the video frame has been encoded, the method includes periodically determining whether the amount of intraframe encoded information for the frame achieves a first threshold, and when the first threshold is achieved, encoding the remainder of the video frame using only intraframe encoding. The method may include determining whether a lower second threshold is achieved based on relative complexity of the frame and quantization. The method may include performing similar comparisons on a slice by slice basis in which any one or more of the processing devices skips motion estimation and interframe encoding for corresponding video slices. A video encoder is disclosed which includes multiple processing devices and a shared memory.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: May 27, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yong Yan, Erez Steinberg, Yehuda Yitschak
  • Patent number: 8711154
    Abstract: Embodiments are disclosed for a system and method for parallel processing of video signals. A multi-core processor is used to establish a master-slave relationship between a first processing core and a plurality of individual processing cores. Shared memory is used to store data and control messages. A plurality of individual private memories are associated with each of the individual processing cores; and control logic is used to establish a master-slave protocol for using the plurality of individual cores to process video data. The master processing core is operable to balance the video data processing load among the individual slave processing cores.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: April 29, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Erez Steinberg, Yaniv Klein, Yehuda Yitschak, Srirama Rao Garikipati, Rajeev Tiwari, Yong Yan
  • Publication number: 20130251031
    Abstract: A method for bit rate control within a scalable video coding system is described. The method comprises, for an access unit within a scalable encoded video bit stream, determining a bit budget for at least one spatial dependence layer within the scalable encoded video bit stream, and calculating at least one quantization parameter value for encoding the at least one spatial dependence layer based at least partly on the determined bit budget for the at least one spatial dependence layer.
    Type: Application
    Filed: November 25, 2010
    Publication date: September 26, 2013
    Inventors: Yehuda Yitschak, Yaniv Klein, Erez Steinberg
  • Publication number: 20130148717
    Abstract: The invention pertains to a video processing system for video processing, the video processing system being arranged to assign tasks to least two parallel processing units capable of parallel processing of tasks. The video processing system is further arranged to control at least one storage device to store input video data to be processed, processed video data and a task list of video processing tasks. The video processing system is arranged to provide and/or process video data having a hierarchical enhancement structure comprising at least one basic layer and one or more enhancement layers dependent on the basic layer and/or at least one of the other enhancement layers. It is further arranged to assign at least one task of the task list to one of the parallel processing units; and to update, after the parallel processing unit has processed a task, the task list with information regarding tasks related to at least one enhancement layer dependent on the processed task.
    Type: Application
    Filed: August 26, 2010
    Publication date: June 13, 2013
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yehuda Yitschak, Yaniv Klein, Moshe Nakash, Erez Steinberg
  • Publication number: 20110293019
    Abstract: Video processing system, computer program product and method for decoding an encoded video stream, the method includes: receiving an encoded video stream that comprises a plurality of encoded video frames, each encoded video frame comprises multiple encoded frame portions; and repeating, for each encoded frame portion: providing, to an entropy decoder, different quality level representations of the encoded frame portion and context information generated during an entropy decoding process of different quality level representations of another encoded frame portion; entropy decoding, by the entropy decoder, the different quality level representations of the frame portion based on the context information; wherein the entropy decoding comprises updating the context information; wherein the entropy decoding is selected from a group consisting of context based adaptive binary arithmetic coding (CABAC) and context based variable length coding (CBVLC); and storing the context information.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: FREESCALE SEMICONDUCTOR INC.
    Inventors: Erez Steinberg, Moshe Nakash, Yehuda Yitschak
  • Publication number: 20110293009
    Abstract: Video processing system, computer program product and method for managing an exchange of information between a memory unit and a decoder, the method includes: (a) retrieving, from the memory unit, a first non-zero data structure that comprises only non-zero first transform coefficient groups; wherein first transform coefficient groups are associated with a first quality level; (b) retrieving, from the memory unit, second layer information; (c) processing, by the video decoder, the second layer information and the first non-zero data structure to provide second transform coefficient groups; (c) generating, by the video decoder, a second non-zero data structure that comprises only non-zero second transform coefficient groups; wherein the second non-zero data structure is associated with a second quality level that is higher than the first quality level; (d) generating second non-zero indicators that are indicative of non-zero transform coefficient groups, wherein the second non-zero data structure is associated
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: FREESCALE SEMICONDUCTOR INC.
    Inventors: Erez Steinberg, Moshe Nakash, Yehuda Yitschak
  • Publication number: 20100195733
    Abstract: A method of encoding a video frame is disclosed in which video slices of the video frame are initially encoded in parallel using both interframe encoding and intraframe encoding. Then, after a first predetermined minimum amount of the video frame has been encoded, the method includes periodically determining whether the amount of intraframe encoded information for the frame achieves a first threshold, and when the first threshold is achieved, encoding the remainder of the video frame using only intraframe encoding. The method may include determining whether a lower second threshold is achieved based on relative complexity of the frame and quantization. The method may include performing similar comparisons on a slice by slice basis in which any one or more of the processing devices skips motion estimation and interframe encoding for corresponding video slices. A video encoder is disclosed which includes multiple processing devices and a shared memory.
    Type: Application
    Filed: February 2, 2009
    Publication date: August 5, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yong Yan, Erez Steinberg, Yehuda Yitschak
  • Publication number: 20090307464
    Abstract: Embodiments are disclosed for a system and method for parallel processing of video signals. A multi-core processor is used to establish a master-slave relationship between a first processing core and a plurality of individual processing cores. Shared memory is used to store data and control messages. A plurality of individual private memories are associated with each of the individual processing cores; and control logic is used to establish a master-slave protocol for using the plurality of individual cores to process video data. The master processing core is operable to balance the video data processing load among the individual slave processing cores.
    Type: Application
    Filed: June 9, 2008
    Publication date: December 10, 2009
    Inventors: Erez Steinberg, Yaniv Klein, Yehuda Yitschak, Srirama Rao Garikipati, Rajeev Tiwari, Yong Yan